3.7.1.2 DMA Support on ADC
Applications may require continuous sampling of the ADC (4K samples/sec) that may
have considerable load on the CPU. Though using PDB to trigger ADC may reduce some
CPU load, the ADC supports DMA request functionality for higher performance when
the ADC is sampled at a very high rate or cases where PDB is bypassed. The ADC can
trigger the DMA (via DMA req) on conversion completion.
3.7.1.3 ADCx Connections/Channel Assignment
NOTE
As indicated by the following sections, each ADCx_DPx input
and certain ADCx_DMx inputs may operate as single-ended
ADC channels in single-ended mode.
3.7.1.3.1 ADC0 channel assignment
Table 3-41. ADC0 Assignments
ADC Channel
(SC1n[ADCH])
Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0)
00000 DAD0 ADC0_DP0 and ADC0_DM0 ADC0_DP0
00001 DAD1 ADC0_DP1 and ADC0_DM1 ADC0_DP1
00010 DAD2 ADC0_DP2 and ADC0_DM2 ADC0_DP2
00011 DAD3 ADC0_DP3 and ADC0_DM3 ADC0_DP3
00100
1
AD4a Reserved Reserved
00101
1
AD5a Reserved Reserved
00110
1
AD6a Reserved Reserved
00111
1
AD7a Reserved Reserved
00100
1
AD4b Reserved ADC0_SE4b
00101
1
AD5b Reserved ADC0_SE5b
00110
1
AD6b Reserved ADC0_SE6b
00111
1
AD7b Reserved ADC0_SE7b
01000 AD8 Reserved ADC0_SE8
01001 AD9 Reserved ADC0_SE9
01010 AD10 Reserved Reserved
01011 AD11 Reserved Reserved
01100 AD12 Reserved ADC0_SE12
01101 AD13 Reserved ADC0_SE13
01110 AD14 Reserved ADC0_SE14
01111 AD15 Reserved ADC0_SE15
10000 AD16 Reserved ADC0_SE16
Table continues on the next page...
Analog
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
98 NXP Semiconductors
To Next Page
Loading...
Need help?
General
