Table 3-41. ADC0 Assignments (continued)
ADC Channel
(SC1n[ADCH])
Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0)
10001 AD17 Reserved ADC0_SE17
10010 AD18 Reserved ADC0_SE18
10011 AD19 Reserved ADC0_DM0
10100 AD20 Reserved ADC0_DM1
10101 AD21 Reserved ADC0_SE21
10110 AD22 Reserved ADC0_SE22
10111 AD23 Reserved 12-bit DAC0 Output/ADC0_SE23
11000 AD24 Reserved Reserved
11001 AD25 Reserved Reserved
11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E)
11011 AD27 Bandgap (Diff) Bandgap (S.E)
2
11100 AD28 Reserved Reserved
11101 AD29 -VREFH (Diff) VREFH (S.E)
11110 AD30 Reserved VREFL
11111 AD31 Module Disabled Module Disabled
1. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter
for details.
2. This is the PMC bandgap 1V reference voltage and not the VREF module 1.2 V reference voltage. Prior to reading from
this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device
data sheet for the bandgap voltage (V
BG
) specification.
3.7.1.3.2 ADC1 channel assignment
Table 3-42. ADC1 Assignments
ADC Channel
(SC1n[ADCH])
Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0)
00000 DAD0 ADC1_DP0 and ADC1_DM0 ADC1_DP0
00001 DAD1 ADC1_DP1 and ADC1_DM1 ADC1_DP1
00010 DAD2 Reserved Reserved
00011 DAD3 ADC1_DP3 and ADC1_DM3 ADC1_DP3
00100
1
AD4a Reserved ADC1_SE4a
00101
1
AD5a Reserved ADC1_SE5a
00110
1
AD6a Reserved ADC1_SE6a
00111
1
AD7a Reserved ADC1_SE7a
00100
1
AD4b Reserved ADC1_SE4b
00101
1
AD5b Reserved ADC1_SE5b
00110
1
AD6b Reserved ADC1_SE6b
00111
1
AD7b Reserved ADC1_SE7b
01000 AD8 Reserved ADC1_SE8
Table continues on the next page...
Chapter 3 Chip Configuration
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 99
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