NXP Semiconductors K22F series User Manual

end
begin
= 1
= 0
end
end
end
end
end
= 1
= 0
= 1
= 1
= 0
= 0
= 1
INVCTRL is updated
by software trigger
software
trigger
hardware
trigger
INVCTRL is updated
by hardware trigger
enhanced PWM synchronization
update INVCTRL register by
PWM synchronization
update INVCTRL register at
each rising edge of system clock
= yes
0 =
1 =
0 =
0 =
no =
1 =
INVC
bit ?
SYNCMODE
bit ?
rising edge
of system
clock ?
update INVCTRL
with its buffer value
update INVCTRL
with its buffer value
HWINVC
bit ?
TRIGn
bit ?
wait hardware trigger n
update INVCTRL
with its buffer value
HWTRIGMODE
bit ?
clear TRIGn bit
SWINVC
bit ?
SWSYNC
bit ?
Figure 39-56. INVCTRL register synchronization flowchart
39.4.11.9
SWOCTRL register synchronization
The SWOCTRL register synchronization updates the SWOCTRL register with its buffer
value.
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
984 NXP Semiconductors

NXP Semiconductors K22F series Specifications

General

Brand	NXP Semiconductors
Model	K22F series
Category	Controller
Language	English