The CHnOC bit enables the software output control for a specific channel output and the
CHnOCV selects the value that is forced to this channel output.
Both CHnOC and CHnOCV bits in SWOCTRL register are buffered and updated with
their buffer value according to SWOCTRL register synchronization.
The following figure shows the channels (n) and (n+1) outputs signals when the software
output control is used. In this case the channels (n) and (n+1) are set to Combine and
Complementary mode.
channel (n+1) match
FTM counter
channel (n) match
channel (n) output
after the software
output control
channel (n+1) output
after the software
output control
CH(n)OC buffer
CH(n+1)OC buffer
CH(n)OC bit
CH(n+1)OC bit
NOTE
CH(n)OCV = 1 and CH(n+1)OCV = 0.
SWOCTRL register synchronization
SWOCTRL register synchronization
write to SWOCTRL register write to SWOCTRL register
Figure 39-65. Example of software output control in Combine and Complementary mode
Software output control forces the following values on channels (n) and (n+1) when the
COMP bit is zero.
Table 39-8. Software ouput control behavior when (COMP = 0)
CH(n)OC CH(n+1)OC CH(n)OCV CH(n+1)OCV Channel (n) Output Channel (n+1) Output
0 0 X X is not modified by SWOC is not modified by SWOC
1 1 0 0 is forced to zero is forced to zero
1 1 0 1 is forced to zero is forced to one
1 1 1 0 is forced to one is forced to zero
1 1 1 1 is forced to one is forced to one
Software output control forces the following values on channels (n) and (n+1) when the
COMP bit is one.
Chapter 39 FlexTimer Module (FTM)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 991
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