UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 305 of 841
NXP Semiconductors
UM10360
Chapter 14: LPC176x/5x UART0/2/3
The UARTn RDA interrupt (UnIIR[3:1] = 010) shares the second level priority with the CTI
interrupt (UnIIR[3:1] = 110). The RDA is activated when the UARTn Rx FIFO reaches the
trigger level defined in UnFCR[7:6] and is reset when the UARTn Rx FIFO depth falls
below the trigger level. When the RDA interrupt goes active, the CPU can read a block of
data defined by the trigger level.
The CTI interrupt (UnIIR[3:1] = 110) is a second level interrupt and is set when the UARTn
Rx FIFO contains at least one character and no UARTn Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UARTn Rx FIFO activity (read or write of UARTn RSR) will
clear the interrupt. This interrupt is intended to flush the UARTn RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
wished to send a 105 character message and the trigger level was 10 characters, the
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
[1] Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
[2] For details see Section 14.4.8 “
UARTn Line Status Register (U0LSR - 0x4000 C014, U2LSR -
0x4009 8014, U3LSR - 0x4009 C014)”
[3] For details see Section 14.4.1 “UARTn Receiver Buffer Register (U0RBR - 0x4000 C000, U2RBR -
0x4009 8000, U3RBR - 0x4009 C000 when DLAB = 0)”
[4] For details see Section 14.4.5 “UARTn Interrupt Identification Register (U0IIR - 0x4000 C008, U2IIR -
0x4009 8008, U3IIR - 0x4009 C008)” and Section 14.4.2 “UARTn Transmit Holding Register (U0THR -
0x4000 C000, U2THR - 0x4009 8000, U3THR - 0x4009 C000 when DLAB = 0)”
The UARTn THRE interrupt (UnIIR[3:1] = 001) is a third level interrupt and is activated
when the UARTn THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UARTn THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the UnTHR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
UnTHR without a THRE interrupt to decode and service. A THRE interrupt is set
Table 277: UARTn Interrupt Handling
U0IIR[3:0]
value
[1]
Priority Interrupt
Type
Interrupt Source Interrupt Reset
0001 - None None -
0110 Highest RX Line
Status / Error
OE
[2]
or PE
[2]
or FE
[2]
or BI
[2]
UnLSR Read
[2]
0100 Second RX Data
Available
Rx data available or trigger level reached in FIFO
(UnFCR0=1)
UnRBR Read
[3]
or UARTn
FIFO drops below trigger level
1100 Second Character
Time-out
indication
Minimum of one character in the Rx FIFO and no
character input or removed during a time period
depending on how many characters are in FIFO and
what the trigger level is set at (3.5 to 4.5 character
times).
The exact time will be:
[(word length)
7 - 2] 8 + [(trigger level - number of
characters)
8 + 1] RCLKs
UnRBR Read
[3]
0010 Third THRE THRE
[2]
UnIIR Read (if source of
interrupt) or THR write
[4]
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