UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 42 of 841
NXP Semiconductors
UM10360
Chapter 4: LPC176x/5x Clocking and power control
The PLL0 output frequency (when PLL0 is both active and connected) is given by:
F
CCO
= (2 M F
IN
) / N
PLL inputs and settings must meet the following:
• F
IN
is in the range of 32 kHz to 50 MHz.
• F
CCO
is in the range of 275 MHz to 550 MHz.
The equation can be solved for other PLL parameters:
M = (F
CCO
N) / (2 F
IN
)
N = (2 M F
IN
) / F
CCO
F
IN
= (F
CCO
N) / (2 M)
Allowed values for M:
At higher oscillator frequencies, in the MHz range, values of M from 6 through 512 are
allowed. This supports the entire useful range of both the main oscillator and the IRC.
For lower frequencies, specifically when the RTC is used to clock PLL0, a set of 65
additional M values have been selected for supporting baud rate generation, CAN
operation, and obtaining integer MHz frequencies. These values are shown in Table 26
.
Table 25. PLL frequency parameter
Parameter Description
F
IN
the frequency of PLLCLKIN from the Clock Source Selection Multiplexer.
F
CCO
the frequency of the PLLCLK (output of the PLL Current Controlled Oscillator)
N PLL0 Pre-divider value from the NSEL0 bits in the PLL0CFG register (PLL0CFG
NSEL0 field + 1). N is an integer from 1 through 32.
M PLL0 Multiplier value from the MSEL0 bits in the PLL0CFG register (PLL0CFG
MSEL0 field + 1). Not all potential values are supported. See below.
F
REF
PLL internal reference frequency, F
IN
divided by N.
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