UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 633 of 841
NXP Semiconductors
UM10360
Chapter 32: LPC176x/5x Flash memory interface and programming
Note that the first entry in the command table is the IAP command, followed by any
required command parameters, starting with Param0. The first entry in the output table is
the Return Code, followed by any other results, starting with Result0.
As per the ARM specification (The ARM Thumb Procedure Call Standard SWS ESPC
0002 A-05) up to 4 parameters can be passed in the r0, r1, r2 and r3 registers
respectively. Additional parameters are passed on the stack. Up to 4 parameters can be
returned in the r0, r1, r2 and r3 registers respectively. Additional parameters are returned
indirectly via memory. Some of the IAP calls require more than 4 parameters. If the ARM
suggested scheme is used for the parameter passing/returning then it might create
problems due to difference in the C compiler implementation from different vendors. The
suggested parameter passing scheme reduces such risk.
The flash memory is not accessible during a write or erase operation. IAP commands,
which results in a flash write/erase operation, use 32 bytes of space in the top portion of
the on-chip RAM for execution. The user program should not be use this space if IAP flash
programming is permitted in the application.
Table 588. IAP Command Summary
IAP Command Command Code Described in
Prepare sector(s) for write operation 50
10
Table 589
Copy RAM to Flash 51
10
Table 590
Erase sector(s) 52
10
Table 591
Blank check sector(s) 53
10
Table 592
Read part ID 54
10
Table 593
Read Boot Code version 55
10
Table 594
Read device serial number 58
10
Table 595
Compare 56
10
Table 596
Reinvoke ISP 57
10
Table 597
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