UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 72 of 841
NXP Semiconductors
UM10360
Chapter 5: LPC176x/5x Flash accelerator
If a flash instruction fetch and a flash data access from the CPU occur at the same time,
the multilayer matrix gives precedence to the data access. This is because a stalled data
access always slows down execution, while a stalled instruction fetch often does not.
When the flash data access is concluded, any flash fetch or prefetch that had been in
progress is re-initiated.
Branches and other program flow changes cause a break in the sequential flow of
instruction fetches described above. Buffer replacement strategy in the flash accelerator
attempts to maximize the chances that potentially reusable information is retained until it
is needed again.
If an attempt is made to write directly to the flash memory without using the normal flash
programming interface (via Boot ROM function calls), the flash accelerator generates an
error condition. The CPU treats this error as a data abort. The GPDMA handles error
conditions as described in Section 31.4.1.6.3
.
When an Instruction Fetch is not satisfied by existing contents of the buffer array, nor has
a prefetch been initiated for that flash line, the CPU will be stalled while a fetch is initiated
for the related 128-bit flash line. If a prefetch has been initiated but not yet completed, the
CPU is stalled for a shorter time since the required flash access is already in progress.
Typically, a flash prefetch is begun whenever an access is made to a just prefetched
address, or to a buffer whose immediate successor is not already in another buffer. A
prefetch in progress may be aborted by a data access, in order to minimize CPU stalls.
A prefetched flash line is latched within the flash memory, but the flash accelerator does
not capture the line in a buffer until the CPU presents an address that is contained within
the prefetched flash line. If the core presents an instruction address that is not already
buffered and is not contained in the prefetched flash line, the prefetched line will be
discarded.
Some special cases include the possibility that the CPU will request a data access to an
address already contained in an instruction buffer. In this case, the data will be read from
the buffer as if it was a data buffer. The reverse case, if the CPU requests an instruction
address that can be satisfied from an existing data buffer, causes the instruction to be
supplied from the data buffer, and the buffer to be changed into an instruction buffer. This
causes the buffer to be handled differently when the flash accelerator is determining which
buffer is to be overwritten next.
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