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UM10360
All informatio
n provided in thi
s document is su
bject to legal dis
claimers.
© NXP B.V
.
2013. All rights rese
rved.
User manual
Rev
. 3
— 20 December 2013
745 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Co
rtex-M3 user guide
__ldrex((volati
le char *) 0xFF);
744
746
Table of Contents
Chapter 1: Lpc176X/5X Introductory Information
4
Introduction
4
Features
5
Applications
7
Ordering Information
8
Part Options Summary
8
Simplified Block Diagram
9
Chapter 35 : Supplementary Information
10
Architectural Overview
10
ARM Cortex-M3 Processor
10
Cortex-M3 Configuration Options
10
System Options
10
Debug Related Options
11
On-Chip Flash Memory System
11
On-Chip Static RAM
11
Block Diagram
12
Chapter 2: Lpc176X/5X Memory Map
13
Memory Map and Peripheral Addressing
13
Memory Maps
13
APB Peripheral Addresses
15
Memory Re-Mapping
16
Boot ROM Re-Mapping
16
AHB Arbitration
16
Bus Fault Exceptions
16
Chapter 3: Lpc176X/5X System Control
18
Introduction
18
Pin Description
18
Register Description
19
Reset
19
Reset Source Identification Register (RSID - 0X400F C180)
22
Brown-Out Detection
23
External Interrupt Inputs
24
Register Description
25
0X400F C140
25
0X400F C148)
26
0X400F C14C)
27
Other System Controls and Status Flags
29
System Controls and Status Register (SCS - 0X400F C1A0)
29
Chapter 4: Lpc176X/5X Clocking and Power Control
30
Summary of Clocking and Power Control Functions
30
Register Description
31
Oscillators
32
Internal RC Oscillator
32
Main Oscillator
32
RTC Oscillator
34
Clock Source Selection Multiplexer
35
Clock Source Select Register (CLKSRCSEL - 0X400F C10C)
35
PLL0 (Phase Locked Loop 0)
36
PLL0 Operation
36
PLL0 and Startup/Boot Code Interaction
36
PLL0 Register Description
37
PLL0 Control Register (PLL0CON - 0X400F C080)
37
PLL0 Configuration Register (PLL0CFG - 0X400F C084)
38
PLL0 Status Register (PLL0STAT - 0X400F C088)
39
PLL0 Interrupt: PLOCK0
40
PLL0 Modes
40
PLL0 Feed Register (PLL0FEED - 0X400F C08C)
41
PLL0 and Power-Down Mode
41
PLL0 Frequency Calculation
41
Procedure for Determining PLL0 Settings
43
Examples of PLL0 Settings
44
Example 1
44
Example 2
44
Example 3
45
PLL0 Setup Sequence
47
PLL1 (Phase Locked Loop 1)
48
PLL1 Register Description
48
PLL1 Control Register
48
C0A0)
49
PLL1 Configuration Register (PLL1CFG - 0X400F C0A4)
50
PLL1 Status Register (PLL1STAT - 0X400F C0A8)
50
PLL1 Modes
51
PLL1 Interrupt: PLOCK1
51
PLL1 Feed Register
52
C0Ac)
52
PLL1 and Power-Down Mode
52
PLL1 Frequency Calculation
53
Procedure for Determining PLL1 Settings
53
Clock Dividers
55
CPU Clock Configuration Register (CCLKCFG - 0X400F C104)
55
USB Clock Configuration Register (USBCLKCFG - 0X400F C108)
56
Peripheral Clock Selection Registers 0 and 1
57
Power Control
59
Sleep Mode
59
Deep Sleep Mode
59
Power-Down Mode
60
Deep Power-Down Mode
61
Peripheral Power Control
61
Register Description
61
Power Mode Control Register (PCON - 0X400F C0C0)
62
Encoding of Reduced Power Modes
63
Wake-Up from Reduced Power Modes
63
Power Control for Peripherals Register (PCONP - 0X400F C0C4)
63
Power Control Usage Notes
65
Power Domains
65
Wake-Up Timer
66
External Clock Output Pin
67
Clock Output Configuration Register
67
Chapter 5: Lpc176X/5X Flash Accelerator
69
Introduction
69
Flash Accelerator Blocks
69
Flash Memory Bank
69
Flash Programming Issues
70
Register Description
70
Flash Accelerator Configuration Register
71
Operation
71
Chapter 6: Lpc176X/5X Nested Vectored Interrupt Controller (NVIC)
73
Features
73
Description
73
Interrupt Sources
73
Vector Table Remapping
76
Examples
76
Register Description
77
Interrupt Set-Enable Register 0 Register (ISER0 - 0Xe000 E100)
78
Interrupt Set-Enable Register 1 Register (ISER1 - 0Xe000 E104)
79
Interrupt Clear-Enable Register 0 (ICER0 - 0Xe000 E180)
80
Interrupt Clear-Enable Register 1 Register (ICER1 - 0Xe000 E184)
81
Interrupt Set-Pending Register 0 Register (ISPR0 - 0Xe000 E200)
82
Interrupt Set-Pending Register 1 Register (ISPR1 - 0Xe000 E204)
83
(ICPR0 - 0Xe000 E280)
84
Interrupt Clear-Pending Register 1 Register
85
(ICPR1 - 0Xe000 E284)
85
Interrupt Active Bit Register 0 (IABR0 - 0Xe000 E300)
86
Interrupt Active Bit Register 1 (IABR1 - 0Xe000 E304)
87
Interrupt Priority Register 0 (IPR0 - 0Xe000 E400)
88
Interrupt Priority Register 1 (IPR1 - 0Xe000 E404)
88
Interrupt Priority Register 2 (IPR2 - 0Xe000 E408)
88
Interrupt Priority Register 3 (IPR3 - 0Xe000 E40C)
89
Interrupt Priority Register 4 (IPR4 - 0Xe000 E410)
89
Interrupt Priority Register 5 (IPR5 - 0Xe000 E414)
89
Interrupt Priority Register 6 (IPR6 - 0Xe000 E418)
90
Interrupt Priority Register 7 (IPR7 - 0Xe000 E41C)
90
Interrupt Priority Register 8 (IPR8 - 0Xe000 E420)
90
Software Trigger Interrupt Register (STIR - 0Xe000 EF00)
91
Chapter 7: Lpc176X/5X Pin Configuration
92
Lpc176X/5X Pin Configuration
92
Lpc176X/5X Pin Description
95
Chapter 8: Lpc176X/5X Pin Connect Block
105
How to Read this Chapter
105
Description
105
Pin Function Select Register Values
105
Multiple Connections
106
Pin Mode Select Register Values
106
Function of PINMODE in Open Drain Mode
107
Register Description
108
Pin Control Module Register Reset Values
108
Pin Function Select Register 0 (PINSEL0 - 0X4002 C000)
109
Pin Function Select Register 1 (PINSEL1 - 0X4002 C004)
109
Pin Function Select Register 2 (PINSEL2 - 0X4002 C008)
110
Pin Function Select Register 3 (PINSEL3 - 0X4002 C00C)
110
Pin Function Select Register 4 (PINSEL4 - 0X4002 C010)
111
Pin Function Select Register 7 (PINSEL7 - 0X4002 C01C)
112
Pin Function Select Register 9 (PINSEL9 - 0X4002 C024)
112
Pin Function Select Register 10 (PINSEL10 - 0X4002 C028)
112
Pin Mode Select Register 0 (PINMODE0 - 0X4002 C040)
113
Pin Mode Select Register 1 (PINMODE1 - 0X4002 C044)
113
Pin Mode Select Register 2 (PINMODE2 - 0X4002 C048)
114
Pin Mode Select Register 3 (PINMODE3 - 0X4002 C04C)
114
Pin Mode Select Register 4 (PINMODE4 - 0X4002 C050)
115
Pin Mode Select Register 7 (PINMODE7 - 0X4002 C05C)
116
Pin Mode Select Register 9 (PINMODE9 - 0X4002 C064)
116
Open Drain Pin Mode Select Register 0 (PINMODE_OD0 - 0X4002 C068)
116
Open Drain Pin Mode Select Register
117
(PINMODE_OD1 - 0X4002 C06C)
117
Open Drain Pin Mode Select Register 2 (PINMODE_OD2 - 0X4002 C070)
118
Open Drain Pin Mode Select Register 3 (PINMODE_OD3 - 0X4002 C074)
119
Open Drain Pin Mode Select Register 4 (PINMODE_OD4 - 0X4002 C078)
119
C Pin Configuration Register (I2CPADCFG - 0X4002 C07C)
120
Chapter 9 : Lpc176X/5X General Purpose Input/Output (GPIO)
121
Basic Configuration
121
Features
121
Digital I/O Ports
121
Interrupt Generating Digital Ports
121
Applications
122
Pin Description
122
Register Description
123
GPIO Port Direction Register Fioxdir (FIO0DIR to FIO4DIR- 0X2009 C000 to 0X2009 C080)
124
GPIO Port Output Set Register Fioxset (FIO0SET to FIO4SET - 0X2009 C018 to 0X2009 C098)
125
GPIO Port Output Clear Register Fioxclr (FIO0CLR to FIO4CLR- 0X2009 C01C to 0X2009 C09C)
127
GPIO Port Pin Value Register Fioxpin (FIO0PIN to FIO4PIN- 0X2009 C014 to 0X2009 C094)
128
Fast GPIO Port Mask Register Fioxmask (FIO0MASK to FIO4MASK - 0X2009 C010 to 0X2009 C090)
130
GPIO Interrupt Registers
132
GPIO Overall Interrupt Status Register (Iointstatus - 0X4002 8080)
132
GPIO Interrupt Enable for Port 0 Rising Edge (Io0Intenr - 0X4002 8090)
132
GPIO Interrupt Enable for Port 2 Rising Edge (Io2Intenr - 0X4002 80B0)
133
GPIO Interrupt Enable for Port 0 Falling Edge (Io0Intenf - 0X4002 8094)
134
GPIO Interrupt Enable for Port 2 Falling Edge (Io2Intenf - 0X4002 80B4)
135
GPIO Interrupt Status for Port 0 Rising Edge Interrupt (Io0Intstatr - 0X4002 8084)
136
GPIO Interrupt Status for Port 2 Rising Edge Interrupt (Io2Intstatr - 0X4002 80A4)
137
GPIO Interrupt Status for Port 0 Falling Edge Interrupt (Io0Intstatf - 0X4002 8088)
137
GPIO Interrupt Status for Port 2 Falling Edge Interrupt (Io2Intstatf - 0X4002 80A8)
138
GPIO Interrupt Clear Register for Port 0 (Io0Intclr - 0X4002 808C)
139
GPIO Interrupt Clear Register for Port 2 (Io2Intclr - 0X4002 80AC)
140
GPIO Usage Notes
141
Example: an Instantaneous Output of 0S and 1S on a GPIO Port
141
Writing to FIOSET/FIOCLR Vs. FIOPIN
141
Chapter 10: Lpc176X/5X Ethernet
142
Basic Configuration
142
Introduction
142
Features
143
Architecture and Operation
144
DMA Engine Functions
145
Overview of DMA Operation
145
Ethernet Packet
146
Overview
147
Partitioning
147
Example PHY Devices
148
Pin Description
148
Registers and Software Interface
149
Register Map
149
Ethernet MAC Register Definitions
151
MAC Configuration Register 1 (MAC1 - 0X5000 0000)
151
MAC Configuration Register 2 (MAC2 - 0X5000 0004)
151
Back-To-Back Inter-Packet-Gap Register (IPGT - 0X5000 0008)
153
Non Back-To-Back Inter-Packet-Gap Register (IPGR - 0X5000 000C)
153
Collision Window / Retry Register (CLRT - 0X5000 0010)
154
Maximum Frame Register (MAXF - 0X5000 0014)
154
PHY Support Register (SUPP - 0X5000 0018)
154
Test Register (TEST - 0X5000 001C)
154
MII Mgmt Configuration Register (MCFG - 0X5000 0020)
155
MII Mgmt Command Register
156
0X5000 0024)
156
MII Mgmt Address Register
156
0X5000 0028)
156
MII Mgmt Write Data Register
156
0X5000 002C)
156
MII Mgmt Read Data Register
157
0X5000 0030)
157
MII Mgmt Indicators Register
157
0X5000 0034)
157
Station Address 0 Register
158
Station Address 1 Register
158
Station Address 2 Register
158
Control Register Definitions
159
Command Register (Command - 0X5000 0100)
159
Status Register (Status - 0X5000 0104)
159
Receive Descriptor Base Address Register (Rxdescriptor - 0X5000 0108)
160
Receive Status Base Address Register (Rxstatus - 0X5000 010C)
160
Receive Number of Descriptors Register (Rxdescriptor - 0X5000 0110)
160
Receive Produce Index Register (Rxproduceindex - 0X5000 0114)
161
Receive Consume Index Register (Rxconsumeindex - 0X5000 0118)
161
Transmit Descriptor Base Address Register (Txdescriptor - 0X5000 011C)
162
Transmit Status Base Address Register (Txstatus - 0X5000 0120)
162
Transmit Number of Descriptors Register (Txdescriptornumber - 0X5000 0124)
162
Transmit Produce Index Register (Txproduceindex - 0X5000 0128)
163
Transmit Consume Index Register (Txconsumeindex - 0X5000 012C)
163
Transmit Status Vector 0 Register
163
0X5000 0158)
163
Transmit Status Vector 1 Register
164
0X5000 015C)
164
Receive Status Vector Register
165
0X5000 0160)
165
Flow Control Counter Register (Flowcontrolcounter - 0X5000 0170)
166
Flow Control Status Register
166
0X5000 0174)
166
Receive Filter Register Definitions
167
Receive Filter Control Register
167
0X5000 0200)
167
Receive Filter Wol Status Register
167
Receive Filter Wol Clear Register (Rxfilterwolclear - 0X5000 0208)
168
Hash Filter Table Lsbs Register (Hashfilterl - 0X5000 0210)
168
Hash Filter Table Msbs Register
169
0X5000 0214)
169
Module Control Register Definitions
169
Interrupt Status Register
169
0X5000 0FE0)
169
Interrupt Enable Register
170
0X5000 0FE4)
170
0Fe8)
170
Interrupt Set Register (Intset - 0X5000 0FEC)
171
Power-Down Register
172
0X5000 0FF4)
172
Descriptor and Status Formats
173
Receive Descriptors and Statuses
173
Transmit Descriptors and Statuses
176
Ethernet Block Functional Description
178
Overview
178
AHB Interface
179
Interrupts
179
Direct Memory Access (DMA)
179
Initialization
182
Transmit Process
183
Receive Process
189
Transmission Retry
195
Status Hash CRC Calculations
195
Duplex Modes
196
IEE 802.3/Clause 31 Flow Control
196
Half-Duplex Mode Backpressure
198
Receive Filtering
199
Power Management
201
Wake-Up on LAN
201
Enabling and Disabling Receive and Transmit
203
Transmission Padding and CRC
205
Huge Frames and Frame Length Checking
206
Statistics Counters
206
MAC Status Vectors
206
Reset
207
Ethernet Errors
208
AHB Bandwidth
209
DMA Access
209
Types of CPU Access
210
Overall Bandwidth
210
CRC Calculation
212
Chapter 11 : Lpc176X/5X USB Device Controller
214
How to Read this Chapter
214
Basic Configuration
214
Introduction
214
Features
215
Fixed Endpoint Configuration
215
Functional Description
216
Analog Transceiver
217
Serial Interface Engine (SIE)
217
Endpoint RAM (EP_RAM)
217
EP_RAM Access Control
217
DMA Engine and Bus Master Interface
218
Register Interface
218
Softconnect
218
Goodlink
218
Operational Overview
218
Pin Description
219
Clocking and Power Management
219
Power Requirements
219
Clocks
219
Power Management Support
220
Remote Wake-Up
221
Register Description
221
Clock Control Registers
222
USB Clock Control Register
222
0X5000 CFF4)
222
USB Clock Status Register
223
Cff8)
223
Device Interrupt Registers
223
USB Interrupt Status Register
223
0X5000 C1C0)
223
USB Device Interrupt Status Register
224
(Usbdevintst - 0X5000 C200)
224
USB Device Interrupt Enable Register (Usbdevinten - 0X5000 C204)
225
USB Device Interrupt Clear Register (Usbdevintclr - 0X5000 C208)
225
USB Device Interrupt Set Register
226
0X5000 C20C)
226
USB Device Interrupt Priority Register (Usbdevintpri - 0X5000 C22C)
227
Endpoint Interrupt Registers
227
USB Endpoint Interrupt Status Register (Usbepintst - 0X5000 C230)
227
USB Endpoint Interrupt Enable Register (Usbepinten - 0X5000 C234)
228
USB Endpoint Interrupt Clear Register (Usbepintclr - 0X5000 C238)
229
USB Endpoint Interrupt Set Register
230
0X5000 C23C)
230
USB Endpoint Interrupt Priority Register (Usbepintpri - 0X5000 C240)
230
Endpoint Realization Registers
231
EP RAM Requirements
231
USB Realize Endpoint Register
232
0X5000 C244)
232
C248)
233
0X5000 C24C)
233
USB Transfer Registers
234
USB Receive Data Register (Usbrxdata - 0X5000 C218)
234
USB Receive Packet Length Register (Usbrxplen - 0X5000 C220)
234
USB Transmit Data Register (Usbtxdata - 0X5000 C21C)
234
USB Transmit Packet Length Register (Usbtxplen - 0X5000 C224)
235
USB Control Register
235
C228)
235
SIE Command Code Registers
236
USB Command Code Register
236
0X5000 C210)
236
USB Command Data Register
236
0X5000 C214)
236
DMA Registers
236
USB DMA Request Status Register
236
0X5000 C250)
236
USB DMA Request Clear Register
237
0X5000 C254)
237
USB DMA Request Set Register
238
0X5000 C258)
238
USB UDCA Head Register
238
C280)
238
USB EP DMA Status Register
238
0X5000 C284)
238
USB EP DMA Enable Register
239
0X5000 C288)
239
USB EP DMA Disable Register
239
0X5000 C28C)
239
USB DMA Interrupt Status Register
239
0X5000 C290)
239
USB DMA Interrupt Enable Register (Usbdmainten - 0X5000 C294)
240
USB End of Transfer Interrupt Status Register (Usbeotintst - 0X5000 C2A0)
240
USB End of Transfer Interrupt Clear Register (Usbeotintclr - 0X5000 C2A4)
241
USB End of Transfer Interrupt Set Register (Usbeotintset - 0X5000 C2A8)
241
USB New DD Request Interrupt Status Register (Usbnddrintst - 0X5000 C2AC)
241
USB New DD Request Interrupt Clear Register (Usbnddrintclr - 0X5000 C2B0)
241
USB New DD Request Interrupt Set Register (Usbnddrintset - 0X5000 C2B4)
241
USB System Error Interrupt Status Register (Usbsyserrintst - 0X5000 C2B8)
242
USB System Error Interrupt Clear Register (Usbsyserrintclr - 0X5000 C2BC)
242
USB System Error Interrupt Set Register (Usbsyserrintset - 0X5000 C2C0)
242
Interrupt Handling
242
Slave Mode
243
DMA Mode
243
Serial Interface Engine Command Description
245
Set Address
246
Byte)
246
Configure Device
246
Set Mode (Command: 0Xf3, Data: Write 1 Byte)
247
Read Current Frame Number (Command: 0Xf5, Data: Read 1 or 2 Bytes)
247
Read Test Register (Command: 0Xfd, Data: Read 2 Bytes)
248
Set Device Status (Command: 0Xfe, Data: Write 1 Byte)
248
Get Device Status (Command: 0Xfe, Data: Read 1 Byte)
249
Get Error Code (Command: 0Xff, Data: Read 1 Byte)
249
Read Error Status (Command: 0Xfb, Data: Read 1 Byte)
250
Select Endpoint (Command: 0X00 - 0X1F, Data: Read 1 Byte (Optional))
250
Select Endpoint/Clear Interrupt (Command: 0X40 - 0X5F, Data: Read 1 Byte)
251
Set Endpoint Status (Command: 0X40 - 0X55, Data: Write 1 Byte (Optional))
252
Clear Buffer
252
(Optional))
252
Validate Buffer
253
None)
253
USB Device Controller Initialization
253
Slave Mode Operation
254
Interrupt Generation
254
Data Transfer for out Endpoints
255
Data Transfer for in Endpoints
255
DMA Operation
255
Transfer Terminology
256
USB Device Communication Area
256
Triggering the DMA Engine
257
The DMA Descriptor
257
Next_Dd_Pointer
258
Dma_Mode
258
Next_Dd_Valid
258
Isochronous_Endpoint
259
Max_Packet_Size
259
Dma_Buffer_Length
259
Dma_Buffer_Start_Addr
259
Dd_Retired
259
Dd_Status
259
Packet_Valid
260
Ls_Byte_Extracted
260
Ms_Byte_Extracted
260
Present_Dma_Count
260
Message_Length_Position
260
Isochronous_Packetsize_Memory_Address
260
Non-Isochronous Endpoint Operation
260
Setting up DMA Transfers
260
Finding DMA Descriptor
261
Transferring the Data
261
Optimizing Descriptor Fetch
261
Ending the Packet Transfer
261
No_Packet DD
262
Isochronous Endpoint Operation
262
Setting up DMA Transfers
262
Finding the DMA Descriptor
262
Transferring the Data
263
OUT Endpoints
263
IN Endpoints
263
DMA Descriptor Completion
263
Isochronous out Endpoint Operation
263
Example
263
Auto Length Transfer Extraction (ATLE) Mode Operation
264
OUT Transfers in ATLE Mode
265
IN Transfers in ATLE Mode
266
Setting up the DMA Transfer
266
Finding the DMA Descriptor
266
Transferring the Data
266
OUT Endpoints
266
IN Endpoints
266
Ending the Packet Transfer
267
OUT Endpoints
267
IN Endpoints
267
Double Buffered Endpoint Operation
267
Bulk Endpoints
267
Isochronous Endpoints
269
Chapter 12 : Lpc176X/5X USB Host Controller
270
How to Read this Chapter
270
Basic Configuration
270
Introduction
270
Features
271
Architecture
271
Interfaces
271
Pin Description
272
USB Host Usage Note
272
Software Interface
272
Register Map
272
USB Host Register Definitions
273
Chapter 13: Lpc176X/5X USB OTG
274
How to Read this Chapter
274
Basic Configuration
274
Introduction
274
Features
274
Architecture
275
Modes of Operation
275
Pin Configuration
276
Connecting the USB Port to an External OTG Transceiver
276
Connecting USB as a Host
277
Connecting USB as Device
277
Register Description
278
USB Interrupt Status Register
278
0X5000 C1C0)
278
OTG Interrupt Status Register (Otgintst - 0X5000 C100)
279
OTG Interrupt Enable Register (Otginten - 0X5000 C104)
279
OTG Interrupt Set Register (Otgintset - 0X5000 C20C)
280
OTG Interrupt Clear Register (Otgintclr - 0X5000 C10C)
280
OTG Status and Control Register (Otgstctrl - 0X5000 C110)
280
OTG Timer Register (Otgtmr - 0X5000 C114)
281
OTG Clock Control Register (Otgclkctrl - 0X5000 CFF4)
281
OTG Clock Status Register (Otgclkst - 0X5000 CFF8)
282
C300)
282
C300)
283
I2C Status Register (I2C_STS - 0X5000 C304)
283
C308)
285
I2C Clock High Register (I2C_CLKHI - 0X5000 C30C)
286
I2C Clock Low Register (I2C_CLKLO - 0X5000 C310)
286
Interrupt Handling
286
HNP Support
287
B-Device: Peripheral to Host Switching
288
Remove D+ Pull-Up
290
Add D+ Pull-Up
291
A-Device: Host to Peripheral HNP Switching
291
Ceiver
294
Discharge VBUS
294
Load and Enable OTG Timer
295
Stop OTG Timer
295
Suspend Host on Port 1
295
Clocking and Power Management
295
Device Clock Request Signals
296
Host Clock Request Signals
297
Power-Down Mode Support
297
USB OTG Controller Initialization
297
Chapter 14 : Lpc176X/5X UART0/2/3
299
Basic Configuration
299
Features
299
Pin Description
300
Register Description
300
Uartn Receiver Buffer Register (U0RBR - 0X4000 C000, U2RBR - 0X4009 8000, U3RBR - 0X4009 C000 When DLAB = 0)
302
Uartn Transmit Holding Register (U0THR - 0X4000 C000, U2THR - 0X4009 8000, U3THR - 0X4009 C000 When DLAB = 0)
302
Uartn Divisor Latch LSB Register
302
When DLAB = 1)
302
Uartn Interrupt Enable Register (U0IER - 0X4000 C004, U2IER - 0X4009 8004, U3IER - 0X4009 C004 When DLAB = 0)
303
Uartn Interrupt Identification Register (U0IIR - 0X4000 C008, U2IIR - 0X4009 8008, U3IIR - 0X4009 C008)
304
Uartn FIFO Control Register (U0FCR - 0X4000 C008, U2FCR - 0X4009 8008, U3FCR - 0X4009 C008)
306
DMA Operation
306
UART Receiver DMA
306
UART Transmitter DMA
307
Uartn Line Control Register (U0LCR - 0X4000 C00C, U2LCR - 0X4009 800C, U3LCR - 0X4009 C00C)
307
Uartn Line Status Register (U0LSR - 0X4000 C014, U2LSR - 0X4009 8014, U3LSR - 0X4009 C014)
307
Uartn Scratch Pad Register (U0SCR - 0X4000 C01C, U2SCR - 0X4009 801C U3SCR - 0X4009 C01C)
309
Uartn Auto-Baud Control Register (U0ACR - 14.5 0X4000 C020, U2ACR - 0X4009 8020, U3ACR - 0X4009 C020)
309
Auto-Baud
310
Auto-Baud Modes
311
Uartn Irda Control Register (U0ICR - 0X4000 C024, U2ICR - 0X4009 8024, U3ICR - 0X4009 C024)
312
Uartn Fractional Divider Register (U0FDR - 0X4000 C028, U2FDR - 0X4009 8028, U3FDR - 0X4009 C028)
313
Baud Rate Calculation
314
Example 2: PCLK = 12 Mhz, BR = 115200
316
Uartn Transmit Enable Register (U0TER - 0X4000 C030, U2TER - 0X4009 8030, U3TER - 0X4009 C030)
316
Architecture
317
Chapter 15: Lpc176X/5X UART1
319
Basic Configuration
319
Features
319
Pin Description
320
Register Description
321
UART1 Receiver Buffer Register (U1RBR - 0X4001 0000, When DLAB = 0)
322
UART1 Transmitter Holding Register (U1THR - 0X4001 0000 When DLAB = 0)
322
UART1 Divisor Latch LSB and MSB Registers (U1DLL - 0X4001 0000 and U1DLM - 0X4001 0004, When DLAB = 1)
322
UART1 Interrupt Enable Register (U1IER - 0X4001 0004, When DLAB = 0)
323
UART1 Interrupt Identification Register (U1IIR - 0X4001 0008)
324
UART1 FIFO Control Register (U1FCR - 0X4001 0008)
326
DMA Operation
326
UART Receiver DMA
327
UART Transmitter DMA
327
UART1 Line Control Register (U1LCR - 0X4001 000C)
327
UART1 Modem Control Register (U1MCR - 0X4001 0010)
327
Auto-Flow Control
328
Auto-RTS
328
Auto-CTS
329
UART1 Line Status Register (U1LSR - 0X4001 0014)
330
UART1 Modem Status Register (U1MSR - 0X4001 0018)
331
UART1 Scratch Pad Register (U1SCR - 0X4001 001C)
332
UART1 Auto-Baud Control Register (U1ACR - 0X4001 0020)
332
Auto-Baud
333
Auto-Baud Modes
334
UART1 Fractional Divider Register (U1FDR - 0X4001 0028)
335
Baud Rate Calculation
336
Example 2: PCLK = 12 Mhz, BR = 115200
338
UART1 Transmit Enable Register (U1TER - 0X4001 0030)
338
UART1 RS485 Control Register (U1RS485CTRL - 0X4001 004C)
339
UART1 RS-485 Address Match Register (U1RS485ADRMATCH - 0X4001 0050)
340
UART1 RS-485 Delay Value Register (U1RS485DLY - 0X4001 0054)
340
RS-485/EIA-485 Modes of Operation
340
RS-485/EIA-485 Normal Multidrop Mode
340
(Nmm)
340
Mode
340
RS-485/EIA-485 Auto Direction Control
341
RS485/EIA-485 Driver Delay Time
341
RS485/EIA-485 Output Inversion
342
Architecture
342
Chapter 16: Lpc176X/5X CAN1/2
344
Basic Configuration
344
CAN Controllers
344
Features
344
General CAN Features
344
CAN Controller Features
345
Acceptance Filter Features
345
Pin Description
345
CAN Controller Architecture
345
APB Interface Block (AIB)
346
Interface Management Logic (IML)
346
Transmit Buffers (TXB)
346
Receive Buffer (RXB)
347
Error Management Logic (EML)
348
Bit Timing Logic (BTL)
348
Bit Stream Processor (BSP)
348
CAN Controller Self-Tests
348
Global Self Test
349
Local Self Test
349
Memory Map of the CAN Block
350
CAN Controller Registers
350
CAN Mode Register (CAN1MOD - 0X4004 4000, CAN2MOD - 0X4004 8000)
352
CAN Command Register (CAN1CMR - 0X4004 X004, CAN2CMR - 0X4004 8004)
354
CAN Global Status Register (CAN1GSR - 0X4004 X008, CAN2GSR - 0X4004 8008)
355
RX Error Counter
357
TX Error Counter
357
CAN Interrupt and Capture Register (CAN1ICR - 0X4004 400C, CAN2ICR - 0X4004 800C)
358
CAN Interrupt Enable Register (CAN1IER - 0X4004 4010, CAN2IER - 0X4004 8010)
361
CAN Bus Timing Register (CAN1BTR -
362
Baud Rate Prescaler
363
Synchronization Jump Width
363
Time Segment 1 and Time Segment 2
363
CAN Error Warning Limit Register (CAN1EWL - 0X4004 4018, CAN2EWL - 0X4004 8018)
363
CAN Status Register (CAN1SR - 0X4004 401C, CAN2SR - 0X4004 801C)
364
CAN Receive Frame Status Register (CAN1RFS - 0X4004 4020, CAN2RFS - 0X4004 8020)
365
ID Index Field
366
CAN Receive Identifier Register (CAN1RID -
366
CAN Receive Data Register a (CAN1RDA -
367
CAN Receive Data Register B (CAN1RDB -
367
CAN Transmit Frame Information Register
367
Automatic Transmit Priority Detection
368
Tx DLC
368
CAN Transmit Identifier Register
369
0X4004 80[34/44/54])
369
CAN Transmit Data Register a (CAN1TDA[1/2/3] - 0X4004 40[38/48/58], CAN2TDA[1/2/3] - 0X4004 80[38/48/58])
369
CAN Transmit Data Register B
370
0X4004 80[3C/4C/5C])
370
CAN Sleep Clear Register (CANSLEEPCLR - 0X400F C110)
370
CAN Wake-Up Flags Register (CANWAKEFLAGS - 0X400F C114)
371
CAN Controller Operation
371
Error Handling
371
Sleep Mode
371
Interrupts
372
Transmit Priority
372
Centralized CAN Registers
372
Central Transmit Status Register (Cantxsr - 0X4004 0000)
373
Central Receive Status Register (Canrxsr - 0X4004 0004)
373
Central Miscellaneous Status Register (CANMSR - 0X4004 0008)
374
Global Acceptance Filter
374
Acceptance Filter Modes
374
Acceptance Filter off Mode
375
Acceptance Filter Bypass Mode
375
Acceptance Filter Operating Mode
375
Fullcan Mode
375
Sections of the ID Look-Up Table RAM
375
ID Look-Up Table RAM
376
Acceptance Filter Registers
378
Acceptance Filter Mode Register (AFMR - 0X4003 C000)
378
Section Configuration Registers
378
Standard Frame Individual Start Address Register (Sff_Sa - 0X4003 C004)
379
Standard Frame Group Start Address Register (Sff_Grp_Sa - 0X4003 C008)
379
Extended Frame Start Address Register
379
0X4003 C00C)
379
Extended Frame Group Start Address Register (Eff_Grp_Sa - 0X4003 C010)
380
End of AF Tables Register (Endoftable - 0X4003 C014)
380
Status Registers
380
LUT Error Address Register (Luterrad - 0X4003 C018)
381
LUT Error Register (Luterr - 0X4003 C01C)
381
Global Fullcaninterrupt Enable Register
381
0X4003 C020)
381
Fullcan Interrupt and Capture Registers (FCANIC0 - 0X4003 C024 and FCANIC1 - 0X4003 C028)
381
Configuration and Search Algorithm
382
Acceptance Filter Search Algorithm
382
Fullcan Mode
383
Fullcan Message Layout
385
Fullcan Interrupts
387
Fullcan Message Interrupt Enable Bit
387
Message Lost Bit and CAN Channel Number
388
Setting the Interrupt Pending Bits
389
Clearing the Interrupt Pending Bits
389
Setting the Message Lost Bit of a Fullcan Message Object (Msglost 63 to 0)
389
Clearing the Message Lost Bit of a Fullcan Message Object (Msglost 63 to 0)
389
Set and Clear Mechanism of the Fullcan Interrupt
389
Scenario 1: Normal Case, no Message Lost . 389 16.16.3.2 Scenario 2: Message Lost
390
By Semaphore Bits
391
Scenario 3.1: Message Gets Overwritten Indicated by Semaphore Bits and Message Lost
391
By Message Lost
392
Scenario 4: Clearing Message Lost Bit
393
Examples of Acceptance Filter Tables and ID Index Values
394
Example 1: Only One Section Is Used
394
Example 2: All Sections Are Used
394
Example 3: more than One but Not All Sections Are Used
394
Configuration Example 4
395
Configuration Example 5
395
Configuration Example 6
396
Explicit Standard Frame Format Identifier Section (11-Bit CAN ID)
397
Group of Standard Frame Format Identifier Section (11-Bit CAN ID)
397
Explicit Extended Frame Format Identifier Section (29-Bit CAN ID, Figure 72)
397
Group of Extended Frame Format Identifier Section (29-Bit CAN ID, Figure 72)
397
Configuration Example 7
398
Fullcan Explicit Standard Frame Format Identifier Section (11-Bit CAN ID)
399
Explicit Standard Frame Format Identifier Section (11-Bit CAN ID)
399
Fullcan Message Object Data Section
399
Look-Up Table Programming Guidelines
400
Chapter 17: Lpc176X/5X SPI
402
Basic Configuration
402
Features
402
SPI Overview
402
Pin Description
403
SPI Data Transfers
403
SPI Peripheral Details
405
General Information
405
Master Operation
405
Slave Operation
406
Exception Conditions
406
Register Description
407
SPI Control Register
407
SPI Status Register
409
SPI Data Register (S0SPDR - 0X4002 0008)
409
SPI Clock Counter Register (S0SPCCR - 0X4002 000C)
409
SPI Test Control Register
410
SPI Test Status Register (SPTSR - 0X4002 0014)
410
SPI Interrupt Register
411
411
411
Architecture
412
Chapter 18: Lpc176X/5X SSP0/1
413
Basic Configuration
413
Features
413
Description
413
Pin Descriptions
414
Bus Description
414
Texas Instruments Synchronous Serial Frame
414
Format
414
SPI Frame Format
415
Control
415
SPI Format with CPOL=0,CPHA=0
416
SPI Format with CPOL=0,CPHA=1
417
SPI Format with CPOL = 1,CPHA = 0
417
SPI Format with CPOL = 1,CPHA = 1
419
Format
419
Setup and Hold Time Requirements on CS with Respect to SK in Microwire Mode
421
Register Description
422
Sspn Control Register 0 (SSP0CR0 -
422
Sspn Control Register 1 (SSP0CR1 -
423
Sspn Data Register (SSP0DR - 0X4008 8008
424
Sspn Status Register (SSP0SR - 0X4008 800C, SSP1SR - 0X4003 000C)
425
Sspn Interrupt Mask Set/Clear Register (SSP0IMSC - 0X4008 8014, SSP1IMSC - 0X4003 0014)
425
Sspn Raw Interrupt Status Register (SSP0RIS -
426
Sspn Masked Interrupt Status Register (SSP0MIS - 0X4008 801C, SSP1MIS - 0X4003 001C)
426
Sspn Interrupt Clear Register (SSP0ICR -
427
Chapter 19 : Lpc176X/5X I2C0/1/2
429
Basic Configuration
429
Features
429
Applications
430
Description
430
I 2 C FAST Mode Plus
431
Pin Description
431
I 2 C Operating Modes
432
Master Transmitter Mode
432
Master Receiver Mode
433
Slave Receiver Mode
434
Slave Transmitter Mode
435
I 2 C Implementation and Operation
435
Input Filters and Output Stages
435
Address Registers, I2ADR0 to I2ADR3
436
Address Mask Registers, I2MASK0 to I2MASK3
437
Comparator
437
Shift Register, I2DAT
437
Arbitration and Synchronization Logic
437
Serial Clock Generator
438
Timing and Control
439
Control Register, I2CONSET and I2CONCLR 439 Status Decoder and Status Register
439
Register Description
440
I C000;2, C000; C000;Ontrol Set Register (IC000;2,C000;ONSET: I C000;2, C000;0, IC000;2,C000;0C000;ONSET - 0X4001 C000;000; I C000;2, C000;1, IC000;2,C000;1C000;ONSET - 0X4005 C000;000; I C000;2, C000;C000;2,, IC000;2,C000;C000;2,C000;ONSET - 0X400A 0000)
441
I2C1DATA_BUFFER- 0X4005 C02C; I 2 C2
441
I C018;2, C018; C018;Ontrol C018;Lear Register (IC018;2,C018;ONC018;LR: I C018;2, C018;0, IC018;2,C018;0C018;ONC018;LR - 0X4001 C018;018; I C018;2, C018;1, IC018;2,C018;1C018;ONC018;LR - 0X4005 C018;018; I C018;2, C018;C018;2,, IC018;2,C018;C018;2,C018;ON
443
I C1,2, C1, Status Register (IC1,2,STAT: I C1,2, C1,0, IC1,2,C1,0STAT - 0X4001 C1,004; I C1,2, C1,1, IC1,2,C1,1STAT - 0X4005 C1,004; I C1,2, C1,C1,2,, IC1,2,C1,C1,2,STAT - 0X400A 0004)
444
I C1,2, C1, Data Register (IC1,2,DAT: I C1,2, C1,0, IC1,2,C1,0DAT - 0X4001 C1,008; I C1,2, C1,1, IC1,2,C1,1DAT - 0X4005 C1,008; I C1,2, C1,C1,2,, IC1,2,C1,C1,2,DAT - 0X400A 0008)
444
I2C1MMCTRL- 0X4005 C01C; I 2 C2
445
I2C2MMCTRL- 0X400A 001C)
445
Interrupt in Monitor Mode
446
Loss of Arbitration in Monitor Mode
446
I2C2DATA_BUFFER- 0X400A 002C)
447
I2C0ADR[0, 1, 2, 3]- 0X4001 C0[0C, 20, 24, 28]; C1, I2C1ADR[0, 1, 2, 3] - Address 0X4005 C0[0C, 20, 24, 28]; I C2, I2C2ADR[0, 1, 2, 3] - Address 0X400A 00[0C, 20, 24, 28])
447
I2C0MASK[0, 1, 2, 3] - 0X4001 C0[30, 34, 38, 3C]; C1, I2C1MASK[0, 1, 2, 3] - Address 0X4005 C0[30, 34, 38, 3C]; I C2, I2C2MASK[0, 1, 2, 3] - Address 0X400A 00[30, 34, 38, 3C])
448
I 2 C SCL HIGH Duty Cycle Register (I2SCLH: I 2 C0, I2C0SCLH - 0X4001 C010; I 2 C1, I2C1SCLH - 0X4005 C010; I 2 C2, I2C2SCLH - 0X400A 0010)
448
C SCL Low Duty Cycle Register (I2SCLL: I I2C0SCLL: 0X4001 C014; I C1 - I2C1SCLL: 0X4005 C014; I C2 - I2C2SCLL: 0X400A 0014)
448
Cycle
449
Details of I C Operating Modes
450
Master Transmitter Mode
451
Master Receiver Mode
453
Slave Receiver Mode
455
Slave Transmitter Mode
457
Detailed State Tables
458
Miscellaneous States
463
I2STAT = 0Xf8
463
I2STAT = 0X00
463
Some Special Cases
463
Simultaneous Repeated START Conditions from Two Masters
463
Data Transfer after Loss of Arbitration
464
Forced Access to the I C-Bus
464
C-Bus Obstructed by a LOW Level on SCL or SDA
464
Bus Error
464
I 2 C State Service Routines
466
Initialization
466
I 2 C Interrupt Service
466
The State Service Routines
466
Adapting State Services to an Application
466
Software Example
467
Initialization Routine
467
Start Master Transmit Function
467
Start Master Receive Function
467
C Interrupt Routine
467
Non Mode Specific States
467
State: 0X00
467
Master States
468
State: 0X08
468
State: 0X10
468
Master Transmitter States
468
State: 0X18
468
State: 0X20
469
State: 0X28
469
State: 0X30
469
State: 0X38
469
Master Receive States
469
State: 0X40
469
State: 0X48
470
State: 0X50
470
State: 0X58
470
Slave Receiver States
470
State: 0X60
470
State: 0X68
471
State: 0X70
471
State: 0X78
471
State: 0X80
471
State: 0X88
472
State: 0X90
472
State: 0X98
472
State: 0Xa0
472
Slave Transmitter States
472
State: 0Xa8
472
State: 0Xb0
473
State: 0Xb8
473
State: 0Xc0
473
State: 0Xc8
473
Chapter 20 : Lpc176X/5X I2S
474
Basic Configuration
474
Features
474
Description
475
Pin Descriptions
476
Register Description
477
Digital Audio Output Register (I2SDAO - 0X400A 8000)
477
Digital Audio Input Register
477
0X400A 8004)
478
Transmit FIFO Register (I2STXFIFO - 0X400A 8008)
478
Receive FIFO Register (I2SRXFIFO - 0X400A 800C)
478
Status Feedback Register (I2SSTATE - 0X400A 8010)
479
DMA Configuration Register 1 (I2SDMA1 - 0X400A 8014)
479
DMA Configuration Register 2 (I2SDMA2 - 0X400A 8018)
480
Interrupt Request Control Register (I2SIRQ - 0X400A 801C)
480
Transmit Clock Rate Register (I2STXRATE - 0X400A 8020)
480
Notes on Fractional Rate Generators
481
Receive Clock Rate Register (I2SRXRATE - 0X400A 8024)
481
Transmit Clock Bit Rate Register (I2STXBITRATE - 0X400A 8028)
482
Receive Clock Bit Rate Register (I2SRXBITRATE - 0X400A 802C)
482
Transmit Mode Control Register (I2STXMODE - 0X400A 8030)
482
Receive Mode Control Register (I2SRXMODE - 0X400A 8034)
483
S Transmit and Receive Interfaces
484
S Operating Modes
485
FIFO Controller
489
Chapter 21: Lpc176X/5X Timer 0/1/2/3
491
Basic Configuration
491
Features
491
Applications
492
Description
492
Pin Description
492
Multiple CAP and MAT Pins
492
Register Description
493
Interrupt Register (T[0/1/2/3]IR - 0X4000 4000, 0X4000 8000, 0X4009 0000, 0X4009 4000)
494
Timer Control Register
494
0X4000 4004, 0X4000 8004, 0X4009 0004, 0X4009 4004)
494
Count Control Register (T[0/1/2/3]CTCR - 0X4000 4070, 0X4000 8070, 0X4009 0070, 0X4009 4070)
495
Timer Counter
496
Prescale Counter Register (T0PC - T3PC, 0X4000 4010, 0X4000 8010, 0X4009 0010, 0X4009 4010)
496
Match Registers (MR0 - MR3)
497
Match Control Register (T[0/1/2/3]MCR - 0X4000 4014, 0X4000 8014, 0X4009 0014, 0X4009 4014)
497
Capture Registers (CR0 - CR1)
498
Capture Control Register (T[0/1/2/3]CCR - 0X4000 4028, 0X4000 8028, 0X4009 0028, 0X4009 4028)
498
External Match Register (T[0/1/2/3]EMR - 0X4000 403C, 0X4000 803C, 0X4009 003C, 0X4009 403C)
498
DMA Operation
499
Example Timer Operation
500
Architecture
501
Chapter 22 : Lpc176X/5X Repetitive Interrupt Timer (RIT)
502
Features
502
Description
502
Register Description
502
RI Compare Value Register (RICOMPVAL - 0X400B 0000)
502
RI Mask Register (RIMASK - 0X400B 0004)
502
RI Control Register (RICTRL - 0X400B 0008)
503
503
503
RI Timer Operation
503
Description
505
Chapter 23 : Lpc176X/5X System Tick Timer
505
Operation
505
Basic Configuration
505
Features
505
Register Description
506
System Timer Control and Status Register (STCTRL - 0Xe000 E010)
506
System Timer Reload Value Register (STRELOAD - 0Xe000 E014)
507
System Timer Current Value Register (STCURR - 0Xe000 E018)
507
System Timer Calibration Value Register (STCALIB - 0Xe000 E01C)
507
Example Timer Calculations
509
Example 1)
509
Example 2)
509
Example 3)
509
Example 4)
509
Chapter 24: Lpc176X/5X Pulse Width Modulator (PWM)
510
Basic Configuration
510
Features
510
Description
511
Sample Waveform with Rules for Single and Double Edge Control
513
Rules for Single Edge Controlled PWM Outputs
514
Rules for Double Edge Controlled PWM Outputs
514
Pin Description
514
Register Description
515
PWM Interrupt Register (PWM1IR - 0X4001 8000)
516
PWM Timer Control Register (PWM1TCR 0X4001 8004)
517
PWM Count Control Register (PWM1CTCR - 0X4001 8070)
517
PWM Match Control Register (PWM1MCR - 0X4001 8014)
518
PWM Capture Control Register (PWM1CCR - 0X4001 8028)
519
PWM Control Register (PWM1PCR - 0X4001 804C)
520
PWM Latch Enable Register (PWM1LER - 0X4001 8050)
521
Chapter 25: Lpc176X/5X Motor Control PWM
523
Introduction
523
Description
523
Pin Description
523
Block Diagram
524
Configuring Other Modules for MCPWM Use
525
General Operation
525
Register Description
526
MCPWM Control Register
527
MCPWM Control Read Address (MCCON - 0X400B 8000)
527
MCPWM Control Set Address
528
0X400B 8004)
528
0X400B 8008)
529
MCPWM Capture Control Register
529
MCPWM Capture Control Read Address (MCCAPCON - 0X400B 800C)
529
MCPWM Capture Control Set Address (MCCAPCON_SET - 0X400B 8010)
530
MCPWM Capture Control Clear Address (MCCAPCON_CLR - 0X400B 8014)
530
MCPWM Interrupt Registers
530
MCPWM Interrupt Enable Read Address
530
MCPWM Interrupt Enable Set Address
531
MCPWM Interrupt Enable Clear Address (MCINTEN_CLR - 0X400B 8058)
531
MCPWM Interrupt Flags Read Address (MCINTF - 0X400B 8068)
531
MCPWM Interrupt Flags Set Address (MCINTF_SET - 0X400B 806C)
531
MCPWM Interrupt Flags Clear Address (MCINTF_CLR - 0X400B 8070)
531
MCPWM Count Control Register
532
MCPWM Count Control Read Address (MCCNTCON - 0X400B 805C)
532
MCPWM Count Control Set Address (MCCNTCON_SET - 0X400B 8060)
533
MCPWM Count Control Clear Address (MCCNTCON_CLR - 0X400B 8064)
533
MCPWM Timer/Counter 0-2 Registers
533
MCPWM Limit 0-2 Registers
534
Match and Limit Write and Operating Registers
534
MCPWM Match 0-2 Registers
535
Match Register in Edge-Aligned Mode
535
Match Register in Center-Aligned Mode
535
And 100% Duty Cycle
535
MCPWM Dead-Time Register (MCDT - 0X400B 803C)
536
MCPWM Commutation Pattern Register (MCCP - 0X400B 8040)
536
MCPWM Capture Registers
537
MCPWM Capture Read Addresses
537
0X400B 8074)
537
PWM Operation
538
Pulse-Width Modulation
538
Edge-Aligned PWM Without Dead-Time
538
Center-Aligned PWM Without Dead-Time
538
Dead-Time Counter
539
Shadow Registers and Simultaneous Updates 540 Fast Abort (ABORT)
540
Capture Events
540
External Event Counting (Counter Mode)
541
Three-Phase DC Mode
541
Three Phase AC Mode
542
Interrupts
543
Chapter 26: Lpc176X/5X Quadrature Encoder Interface (QEI)
544
Basic Configuration
544
Features
544
Introduction
544
Functional Description
546
Input Signals
546
Quadrature Input Signals
546
Digital Input Filtering
547
Position Capture
547
Velocity Capture
547
Velocity Compare
548
Pin Description
549
Register Description
550
Register Summary
550
Control Registers
551
C000)
551
C008)
551
QEI Status Register (QEISTAT - 0X400B C004)
551
Position, Index and Timer Registers
552
C00C)
552
QEI Maximum Position Register (QEIMAXPOS - 0X400B C010)
552
QEI Position Compare Register 0 (CMPOS0 - 0X400B C014)
552
QEI Position Compare Register 1 (CMPOS1 - 0X400B C018)
552
QEI Position Compare Register 2 (CMPOS2 - 0X400B C01C)
553
QEI Index Count Register (INXCNT - 0X400B C020)
553
C024)
553
QEI Timer Reload Register (QEILOAD - 0X400B C028)
553
QEI Timer Register (QEITIME - 0X400B C02C)
553
C030)
554
C034)
554
0X400B C038)
554
C03C)
554
Interrupt Registers
555
QEI Interrupt Status Register (QEIINTSTAT)
555
QEI Interrupt Set Register (QEISET - 0X400B CFEC)
555
QEI Interrupt Clear Register (QEICLR - 0X400B CFE8)
556
QEI Interrupt Enable Register (QEIIE - 0X400B CFE4)
556
QEI Interrupt Enable Set Register (QEIIES - 0X400B CFDC)
557
QEI Interrupt Enable Clear Register (QEIIEC - 0X400B CFD8)
558
Basic Configuration
559
Chapter 27 : Lpc176X/5X Real-Time Clock (RTC) and Backup Registers
559
Features
559
Description
559
Architecture
560
Pin Description
561
Register Description
561
RTC Interrupts
563
Miscellaneous Register Group
563
Interrupt Location Register (ILR - 0X4002 4000)
563
Clock Control Register (CCR - 0X4002 4008)
563
Counter Increment Interrupt Register (CIIR - 0X4002 400C)
564
Alarm Mask Register (AMR - 0X4002 4010)
564
0X4002 405C)
565
0X4002 4058)
565
Consolidated Time Registers
566
Consolidated Time Register 0 (CTIME0 - 0X4002 4014)
566
Consolidated Time Register 1 (CTIME1 - 0X4002 4018)
566
Consolidated Time Register 2 (CTIME2 - 0X4002 401C)
566
Time Counter Group
567
Leap Year Calculation
567
Calibration Register (CALIBRATION - Address 0X4002 4040)
567
Calibration Procedure
568
Backward Calibration
568
Forward Calibration
568
General Purpose Registers
569
General Purpose Registers 0 to 4 (GPREG0 to GPREG4 - Addresses 0X4002 4044 to 0X4002 4054)
569
Alarm Register Group
569
RTC Usage Notes
569
Chapter 28: Lpc176X/5X Watchdog Timer (WDT)
570
Features
570
Applications
570
Description
571
Register Description
571
Watchdog Mode Register (WDMOD - 0X4000 0000)
572
Watchdog Timer Constant Register (WDTC - 0X4000 0004)
573
Watchdog Feed Register (WDFEED - 0X4000 0008)
573
Watchdog Timer Value Register (WDTV - 0X4000 000C)
573
Watchdog Timer Clock Source Selection Register
573
Block Diagram
574
Chapter 29 : Lpc176X/5X Analog-To-Digital Converter (ADC)
575
Basic Configuration
575
Features
575
Description
575
Pin Description
576
Register Description
577
A/D Control Register (AD0CR - 0X4003 4000)
578
A/D Global Data Register (AD0GDR - 0X4003 4004)
579
A/D Interrupt Enable Register (AD0INTEN - 0X4003 400C)
579
A/D Data Registers (AD0DR0 to AD0DR7 - 0X4003 4010 to 0X4003 402C)
580
A/D Status Register (ADSTAT - 0X4003 4030)
581
A/D Trim Register (ADTRIM - 0X4003 4034)
581
Operation
582
Hardware-Triggered Conversion
582
Interrupts
582
Accuracy Vs. Digital Receiver
582
DMA Control
582
Chapter 30 : Lpc176X/5X Digital-To-Analog Converter (DAC)
583
Pin Description
583
Basic Configuration
583
Features
583
Register Description
584
C000)
584
D/A Converter Control Register (DACCTRL - 0X4008 C004)
584
D/A Converter Counter Value Register
585
Operation
585
DMA Counter
585
Double Buffering
585
Chapter 31 : Lpc176X/5X General Purpose DMA (GPDMA)
587
Basic Configuration
587
Introduction
587
Features
587
Functional Description
588
DMA Controller Functional Description
588
AHB Slave Interface
588
Control Logic and Register Bank
589
DMA Request and Response Interface
589
Channel Logic and Channel Register Bank
589
Interrupt Request
589
AHB Master Interface
589
Bus and Transfer Widths
589
Endian Behavior
589
Error Conditions
591
Channel Hardware
592
DMA Request Priority
592
Interrupt Generation
592
DMA System Connections
592
DMA Request Signals
592
DMA Response Signals
592
DMA Request Connections
593
Register Description
594
DMA Interrupt Status Register (Dmacintstat - 0X5000 4000)
596
DMA Interrupt Terminal Count Request Status Register (Dmacinttcstat - 0X5000 4004)
596
DMA Interrupt Terminal Count Request Clear Register (Dmacinttcclear - 0X5000 4008)
596
DMA Interrupt Error Status Register (Dmacinterrstat - 0X5000 400C)
596
DMA Interrupt Error Clear Register (Dmacinterrclr - 0X5000 4010)
597
DMA Raw Interrupt Terminal Count Status Register (Dmacrawinttcstat - 0X5000 4014)
597
DMA Raw Error Interrupt Status Register (Dmacrawinterrstat - 0X5000 4018)
597
DMA Enabled Channel Register (Dmacenbldchns - 0X5000 401C)
598
DMA Software Burst Request Register (Dmacsoftbreq - 0X5000 4020)
598
DMA Software Single Request Register (Dmacsoftsreq - 0X5000 4024)
599
DMA Software Last Burst Request Register (Dmacsoftlbreq - 0X5000 4028)
599
DMA Software Last Single Request Register (Dmacsoftlsreq - 0X5000 402C)
599
DMA Configuration Register (Dmacconfig - 0X5000 4030)
600
DMA Synchronization Register (Dmacsync - 0X5000 4034)
600
DMA Request Select Register (Dmareqsel - 0X400F C1C4)
601
DMA Channel Registers
601
DMA Channel Source Address Registers (Dmaccxsrcaddr - 0X5000 41X0)
602
DMA Channel Destination Address Registers (Dmaccxdestaddr - 0X5000 41X4)
602
DMA Channel Linked List Item Registers (Dmaccxlli - 0X5000 41X8)
602
DMA Channel Control Registers (Dmaccxcontrol - 0X5000 41Xc)
603
Protection and Access Information
603
DMA Channel Configuration Registers (Dmaccxconfig - 0X5000 41X0)
605
Lock Control
607
Transfer Type
607
Using the DMA Controller
608
Programming the DMA Controller
608
Enabling the DMA Controller
608
Disabling the DMA Controller
608
Enabling a DMA Channel
608
Disabling a DMA Channel
608
Disabling a DMA Channel and Losing Data in the FIFO
608
Disabling the DMA Channel Without Losing Data in the FIFO
608
Setting up a New DMA Transfer
608
Halting a DMA Channel
609
Programming a DMA Channel
609
Flow Control
609
Peripheral-To-Memory or Memory-To-Peripheral DMA Flow
610
Peripheral-To-Peripheral DMA Flow
610
Memory-To-Memory DMA Flow
611
Interrupt Requests
611
Hardware Interrupt Sequence Flow
612
Address Generation
612
Word-Aligned Transfers Across a Boundary . 612 Scatter/Gather
612
Linked List Items
613
Programming the DMA Controller for Scatter/Gather DMA
613
Example of Scatter/Gather DMA
613
Chapter 32: Lpc176X/5X Flash Memory Interface and Programming
616
Introduction
616
Features
616
Description
616
Memory Map after any Reset
617
Criterion for Valid User Code
617
Communication Protocol
618
ISP Command Format
618
ISP Response Format
618
ISP Data Format
618
ISP Flow Control
619
ISP Command Abort
619
Interrupts During IAP
619
RAM Used by ISP Command Handler
619
RAM Used by IAP Command Handler
619
Boot Process Flowchart
620
Sector Numbers
621
Code Read Protection (CRP)
622
ISP Commands
624
Unlock <Unlock Code
624
Set Baud Rate <Baud Rate> <Stop Bit
625
Echo <Setting
625
Write to RAM <Start Address> <Number of Bytes
625
Read Memory <Address> <No. of Bytes
626
Prepare Sector(S) for Write Operation <Start Sector Number> <End Sector Number
627
Copy RAM to Flash <Flash Address> <RAM Address> <No of Bytes
627
Go <Address> <Mode
628
Erase Sector(S) <Start Sector Number> <End Sector Number
628
Blank Check Sector(S) <Sector Number> <End Sector Number
629
Read Part Identification Number
629
Read Boot Code Version Number
630
Read Device Serial Number
630
Compare <Address1> <Address2> <No of Bytes
630
ISP Return Codes
631
IAP Commands
632
Prepare Sector(S) for Write Operation
634
Copy RAM to Flash
635
Erase Sector(S)
635
Blank Check Sector(S)
636
Read Part Identification Number
636
Read Boot Code Version Number
636
Read Device Serial Number
637
Compare <Address1> <Address2> <No of Bytes
637
Re-Invoke ISP
637
IAP Status Codes
638
JTAG Flash Programming Interface
638
Flash Signature Generation
639
Register Description for Signature Generation
639
Registers
640
Signature Generation Result Registers
640
0X0X4008 4FE0)
641
0X0X4008 4FE8)
641
Algorithm and Procedure for Signature Generation
642
Signature Generation
642
Content Verification
642
Chapter 33 : Lpc176X/5X JTAG, Serial Wire Debug (SWD), and Trace
643
Features
643
Introduction
643
Description
643
Pin Description
643
Debug Notes
644
JTAG TAP Identification
645
Debug Memory Re-Mapping
645
Memory Mapping Control Register (MEMMAP - 0X400F C040)
645
Chapter 34 : Appendix: Cortex-M3 User Guide
646
ARM Cortex-M3 User Guide: Introduction
646
About the Processor and Core Peripherals
646
System Level Interface
647
Integrated Configurable Debug
647
Cortex-M3 Processor Features and Benefits Summary
648
Cortex-M3 Core Peripherals
648
ARM Cortex-M3 User Guide: Instruction Set
649
Instruction Set Summary
649
Note
649
Intrinsic Functions
652
About the Instruction Descriptions
652
Operands
653
Restrictions When Using PC or SP
653
Flexible Second Operand
653
Constant
653
Register with Optional Shift
654
Shift Operations
654
Asr
655
Note
655
Lsr
655
Lsl
656
Note
656
Ror
656
Rrx
657
Address Alignment
657
PC-Relative Expressions
658
Note
658
Conditional Execution
658
The Condition Flags
659
Condition Code Suffixes
659
Instruction Width Selection
660
Example: Instruction Width Selection
660
Memory Access Instructions
661
Adr
662
Syntax
662
Operation
662
Restrictions
662
Condition Flags
662
Examples
662
LDR and STR, Immediate Offset
663
Syntax
663
Operation
663
Restrictions
664
Condition Flags
664
Examples
665
LDR and STR, Register Offset
666
Syntax
666
Operation
666
Restrictions
666
Condition Flags
667
Examples
667
LDR and STR, Unprivileged
668
Syntax
668
Operation
668
Restrictions
668
Condition Flags
668
Examples
669
LDR, PC-Relative
670
Syntax
670
Operation
670
Restrictions
670
Condition Flags
671
Examples
671
LDM and STM
672
Syntax
672
Operation
672
Restrictions
673
Condition Flags
673
Examples
673
Incorrect Examples
673
PUSH and POP
674
Syntax
674
Operation
674
Restrictions
674
Condition Flags
674
Examples
674
LDREX and STREX
675
Syntax
675
Operation
675
Restrictions
675
Condition Flags
676
Examples
676
Clrex
677
Syntax
677
Operation
677
Condition Flags
677
Examples
677
General Data Processing Instructions
678
ADD, ADC, SUB, SBC, and RSB
679
Syntax
679
Operation
679
Restrictions
679
Note
680
Condition Flags
680
Examples
680
Multiword Arithmetic Examples
680
AND, ORR, EOR, BIC, and ORN
682
Syntax
682
Operation
682
Restrictions
682
Condition Flags
682
Examples
682
ASR, LSL, LSR, ROR, and RRX
684
Syntax
684
Operation
684
Restrictions
684
Condition Flags
685
Examples
685
Clz
686
Syntax
686
Operation
686
Restrictions
686
Condition Flags
686
Examples
686
CMP and CMN
687
Syntax
687
Operation
687
Restrictions
687
Condition Flags
687
Examples
687
MOV and MVN
688
Syntax
688
Operation
688
Restrictions
689
Condition Flags
689
Example
689
Movt
690
Syntax
690
Operation
690
Restrictions
690
Condition Flags
690
Examples
690
REV, REV16, REVSH, and RBIT
691
Syntax
691
Operation
691
Restrictions
691
Condition Flags
691
Examples
691
TST and TEQ
692
Syntax
692
Operation
692
Restrictions
692
Condition Flags
692
Examples
692
Multiply and Divide Instructions
693
MUL, MLA, and MLS
694
Syntax
694
Operation
694
Restrictions
694
Condition Flags
694
Examples
695
UMULL, UMLAL, SMULL, and SMLAL
696
Syntax
696
Operation
696
Restrictions
696
Condition Flags
696
Examples
697
SDIV and UDIV
698
Syntax
698
Operation
698
Restrictions
698
Condition Flags
698
Examples
698
Saturating Instructions
699
SSAT and USAT
699
Syntax
699
Operation
699
Restrictions
700
Condition Flags
700
Examples
700
Bitfield Instructions
701
BFC and BFI
702
Syntax
702
Operation
702
Restrictions
702
Condition Flags
702
Examples
702
SBFX and UBFX
703
Syntax
703
Operation
703
Restrictions
703
Condition Flags
703
Examples
703
SXT and UXT
704
Syntax
704
Operation
704
Restrictions
704
Condition Flags
704
Examples
705
Branch and Control Instructions
706
B, BL, BX, and BLX
707
Syntax
707
Operation
707
Restrictions
708
Condition Flags
708
Examples
708
CBZ and CBNZ
709
Syntax
709
Operation
709
Restrictions
709
Condition Flags
709
Examples
709
Syntax
710
Operation
710
Restrictions
710
Condition Flags
711
Example
711
TBB and TBH
713
Syntax
713
Operation
713
Restrictions
713
Condition Flags
713
Examples
713
Miscellaneous Instructions
715
Bkpt
716
Syntax
716
Operation
716
Condition Flags
716
Examples
716
Cps
717
Syntax
717
Operation
717
Restrictions
717
Condition Flags
717
Examples
717
Dmb
718
Syntax
718
Operation
718
Condition Flags
718
Examples
718
Dsb
719
Syntax
719
Operation
719
Condition Flags
719
Examples
719
Isb
720
Syntax
720
Operation
720
Condition Flags
720
Examples
720
Mrs
721
Syntax
721
Operation
721
Restrictions
721
Condition Flags
721
Examples
721
Msr
722
Syntax
722
Operation
722
Note
722
Restrictions
722
Condition Flags
722
Examples
722
Nop
723
Syntax
723
Operation
723
Condition Flags
723
Examples
723
Sev
724
Syntax
724
Operation
724
Condition Flags
724
Examples
724
Svc
725
Syntax
725
Operation
725
Condition Flags
725
Examples
725
Wfe
726
Syntax
726
Operation
726
Condition Flags
726
Examples
726
Wfi
727
Syntax
727
Operation
727
Condition Flags
727
Examples
727
ARM Cortex-M3 User Guide: Processor
728
Programmers Model
728
Processor Mode and Privilege Levels for Software Execution
728
Stacks
728
Core Registers
729
General-Purpose Registers
730
Stack Pointer
730
Link Register
730
Program Counter
730
Program Status Register
730
Exception Mask Registers
734
CONTROL Register
735
Exceptions and Interrupts
735
Data Types
736
The Cortex Microcontroller Software Interface Standard
736
Memory Model
737
Memory Regions, Types and Attributes
737
Memory System Ordering of Memory Accesses
738
Behavior of Memory Accesses
739
Software Ordering of Memory Accesses
739
Bit-Banding
740
Directly Accessing an Alias Region
742
Directly Accessing a Bit-Band Region
742
Memory Endianness
743
Little-Endian Format
743
Synchronization Primitives
743
Programming Hints for the Synchronization Primitives
744
Exception Model
746
Exception States
746
Exception Types
746
Exception Handlers
748
Vector Table
749
Exception Priorities
749
Interrupt Priority Grouping
750
Exception Entry and Return
750
Exception Entry
751
Exception Return
752
Fault Handling
754
Fault Types
754
Fault Escalation and Hard Faults
755
Fault Status Registers and Fault Address Registers
755
Lockup
756
Power Management
757
Entering Sleep Mode
757
Wait for Interrupt
757
Wait for Event
757
Sleep-On-Exit
758
Wakeup from Sleep Mode
758
Wakeup from WFI or Sleep-On-Exit
758
Wakeup from WFE
758
The Wake-Up Interrupt Controller
758
Power Management Programming Hints
759
ARM Cortex-M3 User Guide: Peripherals
760
About the Cortex-M3 Peripherals
760
Nested Vectored Interrupt Controller
761
The CMSIS Mapping of the Cortex-M3 NVIC Registers
761
Interrupt Set-Enable Registers
762
Interrupt Clear-Enable Registers
762
Interrupt Set-Pending Registers
763
Interrupt Clear-Pending Registers
763
Interrupt Active Bit Registers
764
Interrupt Priority Registers
764
Software Trigger Interrupt Register
765
Level-Sensitive and Pulse Interrupts
765
Hardware and Software Control of Interrupts
766
NVIC Design Hints and Tips
766
NVIC Programming Hints
767
System Control Block
768
The CMSIS Mapping of the Cortex-M3 SCB Registers
768
Auxiliary Control Register
768
About IT Folding
769
CPUID Base Register
769
Interrupt Control and State Register
769
Vector Table Offset Register
771
Application Interrupt and Reset Control Register
772
Binary Point
773
System Control Register
773
Configuration and Control Register
774
System Handler Priority Registers
775
System Handler Priority Register 1
776
System Handler Priority Register 2
776
System Handler Priority Register 3
776
System Handler Control and State Register
776
Caution
777
Configurable Fault Status Register
778
Memory Management Fault Status Register
778
Bus Fault Status Register
779
Usage Fault Status Register
780
Hard Fault Status Register
782
Register
782
Bus Fault Address Register
782
System Control Block Design Hints and Tips
783
System Timer, Systick
784
Systick Control and Status Register
784
Systick Reload Value Register
785
Calculating the RELOAD Value
785
Systick Current Value Register
785
Systick Calibration Value Register
785
Systick Design Hints and Tips
786
Memory Protection Unit
787
MPU Type Register
788
MPU Control Register
789
MPU Region Number Register
790
MPU Region Base Address Register
790
The ADDR Field
791
MPU Region Attribute and Size Register
791
SIZE Field Values
792
MPU Access Permission Attributes
793
MPU Mismatch
794
Updating an MPU Region
794
Words
794
Writes
795
Subregions
796
MPU Design Hints and Tips
797
MPU Configuration for a Microcontroller
797
ARM Cortex-M3 User Guide: Glossary
798
Abbreviations
802
Legal Information
803
Definitions
803
Disclaimers
803
Trademarks
803
Tables
804
Figures
816
Contents
818
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NXP Semiconductors LPC1768 Specifications
General
Brand
NXP Semiconductors
Model
LPC1768
Category
Microcontrollers
Language
English
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