NXP Semiconductors LPC1768

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 835 of 841
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NXP Semiconductors
UM10360
Chapter 35: Supplementary information
30.3 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 583
30.4 Register description . . . . . . . . . . . . . . . . . . . 584
30.4.1 D/A Converter Register (DACR - 0x4008
C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
30.4.2 D/A Converter Control register (DACCTRL -
0x4008 C004). . . . . . . . . . . . . . . . . . . . . . . . 584
30.4.3 D/A Converter Counter Value register
(DACCNTVAL - 0x4008 C008). . . . . . . . . . . 585
30.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
30.5.1 DMA counter . . . . . . . . . . . . . . . . . . . . . . . . 585
30.5.2 Double buffering. . . . . . . . . . . . . . . . . . . . . . 585
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
31.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 587
31.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 587
31.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
31.4 Functional description . . . . . . . . . . . . . . . . . 588
31.4.1 DMA controller functional description . . . . . . 588
31.4.1.1 AHB slave interface . . . . . . . . . . . . . . . . . . . 588
31.4.1.2 Control logic and register bank. . . . . . . . . . . 589
31.4.1.3 DMA request and response interface . . . . . . 589
31.4.1.4 Channel logic and channel register bank . . . 589
31.4.1.5 Interrupt request . . . . . . . . . . . . . . . . . . . . . . 589
31.4.1.6 AHB master interface . . . . . . . . . . . . . . . . . . 589
31.4.1.6.1 Bus and transfer widths . . . . . . . . . . . . . . . . 589
31.4.1.6.2 Endian behavior . . . . . . . . . . . . . . . . . . . . . . 589
31.4.1.6.3 Error conditions . . . . . . . . . . . . . . . . . . . . . . 591
31.4.1.7 Channel hardware . . . . . . . . . . . . . . . . . . . . 592
31.4.1.8 DMA request priority. . . . . . . . . . . . . . . . . . . 592
31.4.1.9 Interrupt generation . . . . . . . . . . . . . . . . . . . 592
31.4.2 DMA system connections . . . . . . . . . . . . . . . 592
31.4.2.1 DMA request signals . . . . . . . . . . . . . . . . . . 592
31.4.2.2 DMA response signals . . . . . . . . . . . . . . . . . 592
31.4.2.3 DMA request connections . . . . . . . . . . . . . . 593
31.5 Register description . . . . . . . . . . . . . . . . . . . 594
31.5.1 DMA Interrupt Status register (DMACIntStat -
0x5000 4000) . . . . . . . . . . . . . . . . . . . . . . . . 596
31.5.2 DMA Interrupt Terminal Count Request Status
register (DMACIntTCStat - 0x5000 4004). . . 596
31.5.3 DMA Interrupt Terminal Count Request Clear
register (DMACIntTCClear - 0x5000 4008) . 596
31.5.4 DMA Interrupt Error Status register
(DMACIntErrStat - 0x5000 400C) . . . . . . . . . 596
31.5.5 DMA Interrupt Error Clear register
(DMACIntErrClr - 0x5000 4010) . . . . . . . . . . 597
31.5.6 DMA Raw Interrupt Terminal Count Status register
(DMACRawIntTCStat - 0x5000 4014). . . . . . 597
31.5.7 DMA Raw Error Interrupt Status register
(DMACRawIntErrStat - 0x5000 4018). . . . . . 597
31.5.8 DMA Enabled Channel register
(DMACEnbldChns - 0x5000 401C). . . . . . . . 598
31.5.9 DMA Software Burst Request register
(DMACSoftBReq - 0x5000 4020) . . . . . . . . . 598
31.5.10 DMA Software Single Request register
(DMACSoftSReq - 0x5000 4024). . . . . . . . . 599
31.5.11 DMA Software Last Burst Request register
(DMACSoftLBReq - 0x5000 4028). . . . . . . . 599
31.5.12 DMA Software Last Single Request register
(DMACSoftLSReq - 0x5000 402C) . . . . . . . 599
31.5.13 DMA Configuration register (DMACConfig -
0x5000 4030) . . . . . . . . . . . . . . . . . . . . . . . . 600
31.5.14 DMA Synchronization register (DMACSync -
0x5000 4034) . . . . . . . . . . . . . . . . . . . . . . . . 600
31.5.15 DMA Request Select register (DMAReqSel -
0x400F C1C4) . . . . . . . . . . . . . . . . . . . . . . . 601
31.5.16 DMA Channel registers . . . . . . . . . . . . . . . . 601
31.5.17 DMA Channel Source Address registers
(DMACCxSrcAddr - 0x5000 41x0). . . . . . . . 602
31.5.18 DMA Channel Destination Address registers
(DMACCxDestAddr - 0x5000 41x4). . . . . . . 602
31.5.19 DMA Channel Linked List Item registers
(DMACCxLLI - 0x5000 41x8). . . . . . . . . . . . 602
31.5.20 DMA channel control registers (DMACCxControl -
0x5000 41xC). . . . . . . . . . . . . . . . . . . . . . . . 603
31.5.20.1 Protection and access information. . . . . . . . 603
31.5.21 DMA Channel Configuration registers
(DMACCxConfig - 0x5000 41x0) . . . . . . . . . 605
31.5.21.1 Lock control . . . . . . . . . . . . . . . . . . . . . . . . . 607
31.5.21.2 Transfer type . . . . . . . . . . . . . . . . . . . . . . . . 607
31.6 Using the DMA controller. . . . . . . . . . . . . . . 608
31.6.1 Programming the DMA controller. . . . . . . . . 608
31.6.1.1 Enabling the DMA controller . . . . . . . . . . . . 608
31.6.1.2 Disabling the DMA controller . . . . . . . . . . . . 608
31.6.1.3 Enabling a DMA channel . . . . . . . . . . . . . . . 608
31.6.1.4 Disabling a DMA channel. . . . . . . . . . . . . . . 608
Disabling a DMA channel and losing data in the
FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Disabling the DMA channel without losing data in
the FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
31.6.1.5 Setting up a new DMA transfer . . . . . . . . . . 608
31.6.1.6 Halting a DMA channel . . . . . . . . . . . . . . . . 609
31.6.1.7 Programming a DMA channel . . . . . . . . . . . 609
31.6.2 Flow control . . . . . . . . . . . . . . . . . . . . . . . . . 609