NXP Semiconductors LPC1768 - Page 840

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User manual Rev. 3 — 20 December 2013 840 of 841
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NXP Semiconductors
UM10360
Chapter 35: Supplementary information
34.3.1.6 The Cortex Microcontroller Software Interface
Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
34.3.2 Memory model . . . . . . . . . . . . . . . . . . . . . . . 737
34.3.2.1 Memory regions, types and attributes. . . . . . 737
34.3.2.2 Memory system ordering of memory
accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
34.3.2.3 Behavior of memory accesses . . . . . . . . . . . 739
34.3.2.4 Software ordering of memory accesses . . . . 739
34.3.2.5 Bit-banding . . . . . . . . . . . . . . . . . . . . . . . . . . 740
34.3.2.5.1 Directly accessing an alias region . . . . . . . . 742
34.3.2.5.2 Directly accessing a bit-band region. . . . . . . 742
34.3.2.6 Memory endianness . . . . . . . . . . . . . . . . . . . 743
34.3.2.6.1 Little-endian format. . . . . . . . . . . . . . . . . . . . 743
34.3.2.7 Synchronization primitives . . . . . . . . . . . . . . 743
34.3.2.8 Programming hints for the synchronization
primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
34.3.3 Exception model. . . . . . . . . . . . . . . . . . . . . . 746
34.3.3.1 Exception states . . . . . . . . . . . . . . . . . . . . . . 746
34.3.3.2 Exception types . . . . . . . . . . . . . . . . . . . . . . 746
34.3.3.3 Exception handlers . . . . . . . . . . . . . . . . . . . . 748
34.3.3.4 Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . 749
34.3.3.5 Exception priorities . . . . . . . . . . . . . . . . . . . . 749
34.3.3.6 Interrupt priority grouping . . . . . . . . . . . . . . . 750
34.3.3.7 Exception entry and return . . . . . . . . . . . . . . 750
34.3.3.7.1 Exception entry. . . . . . . . . . . . . . . . . . . . . . . 751
34.3.3.7.2 Exception return . . . . . . . . . . . . . . . . . . . . . . 752
34.3.4 Fault handling. . . . . . . . . . . . . . . . . . . . . . . . 754
34.3.4.1 Fault types . . . . . . . . . . . . . . . . . . . . . . . . . . 754
34.3.4.2 Fault escalation and hard faults . . . . . . . . . . 755
34.3.4.3 Fault status registers and fault address
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
34.3.4.4 Lockup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
34.3.5 Power management . . . . . . . . . . . . . . . . . . . 757
34.3.5.1 Entering sleep mode. . . . . . . . . . . . . . . . . . . 757
34.3.5.1.1 Wait for interrupt. . . . . . . . . . . . . . . . . . . . . . 757
34.3.5.1.2 Wait for event . . . . . . . . . . . . . . . . . . . . . . . . 757
34.3.5.1.3 Sleep-on-exit . . . . . . . . . . . . . . . . . . . . . . . . 758
34.3.5.2 Wakeup from sleep mode. . . . . . . . . . . . . . . 758
34.3.5.2.1 Wakeup from WFI or sleep-on-exit. . . . . . . . 758
34.3.5.2.2 Wakeup from WFE . . . . . . . . . . . . . . . . . . . . 758
34.3.5.3 The Wake-up Interrupt Controller . . . . . . . . . 758
34.3.5.4 Power management programming hints. . . . 759
34.4 ARM Cortex-M3 User Guide: Peripherals . . 760
34.4.1 About the Cortex-M3 peripherals . . . . . . . . . 760
34.4.2 Nested Vectored Interrupt Controller . . . . . . 761
34.4.2.1 The CMSIS mapping of the Cortex-M3 NVIC
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
34.4.2.2 Interrupt Set-enable Registers . . . . . . . . . . . 762
34.4.2.3 Interrupt Clear-enable Registers. . . . . . . . . . 762
34.4.2.4 Interrupt Set-pending Registers . . . . . . . . . . 763
34.4.2.5 Interrupt Clear-pending Registers . . . . . . . . 763
34.4.2.6 Interrupt Active Bit Registers . . . . . . . . . . . . 764
34.4.2.7 Interrupt Priority Registers . . . . . . . . . . . . . . 764
34.4.2.8 Software Trigger Interrupt Register . . . . . . . 765
34.4.2.9 Level-sensitive and pulse interrupts. . . . . . . 765
34.4.2.9.1 Hardware and software control of interrupts 766
34.4.2.10 NVIC design hints and tips. . . . . . . . . . . . . . 766
34.4.2.10.1 NVIC programming hints . . . . . . . . . . . . . . 767
34.4.3 System control block . . . . . . . . . . . . . . . . . . 768
34.4.3.1 The CMSIS mapping of the Cortex-M3 SCB
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
34.4.3.2 Auxiliary Control Register . . . . . . . . . . . . . . 768
34.4.3.2.1 About IT folding . . . . . . . . . . . . . . . . . . . . . . 769
34.4.3.3 CPUID Base Register . . . . . . . . . . . . . . . . . 769
34.4.3.4 Interrupt Control and State Register . . . . . . 769
34.4.3.5 Vector Table Offset Register . . . . . . . . . . . . 771
34.4.3.6 Application Interrupt and Reset Control
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
34.4.3.6.1 Binary point . . . . . . . . . . . . . . . . . . . . . . . . . 773
34.4.3.7 System Control Register . . . . . . . . . . . . . . . 773
34.4.3.8 Configuration and Control Register . . . . . . . 774
34.4.3.9 System Handler Priority Registers. . . . . . . . 775
34.4.3.9.1 System Handler Priority Register 1 . . . . . . . 776
34.4.3.9.2 System Handler Priority Register 2 . . . . . . . 776
34.4.3.9.3 System Handler Priority Register 3 . . . . . . . 776
34.4.3.10 System Handler Control and State Register 776
Caution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
34.4.3.11 Configurable Fault Status Register . . . . . . . 778
34.4.3.11.1 Memory Management Fault Status Register 778
34.4.3.11.2 Bus Fault Status Register. . . . . . . . . . . . . . 779
34.4.3.11.3 Usage Fault Status Register . . . . . . . . . . . 780
34.4.3.12 Hard Fault Status Register. . . . . . . . . . . . . . 782
34.4.3.13 Memory Management Fault Address
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
34.4.3.14 Bus Fault Address Register . . . . . . . . . . . . . 782
34.4.3.15 System control block design hints and tips . 783
34.4.4 System timer, SysTick . . . . . . . . . . . . . . . . . 784
34.4.4.1 SysTick Control and Status Register . . . . . . 784
34.4.4.2 SysTick Reload Value Register . . . . . . . . . . 785
34.4.4.2.1 Calculating the RELOAD value . . . . . . . . . . 785
34.4.4.3 SysTick Current Value Register . . . . . . . . . . 785
34.4.4.4 SysTick Calibration Value Register . . . . . . . 785
34.4.4.5 SysTick design hints and tips. . . . . . . . . . . . 786
34.4.5 Memory protection unit . . . . . . . . . . . . . . . . 787
34.4.5.1 MPU Type Register . . . . . . . . . . . . . . . . . . . 788
34.4.5.2 MPU Control Register . . . . . . . . . . . . . . . . . 789
34.4.5.3 MPU Region Number Register . . . . . . . . . . 790
34.4.5.4 MPU Region Base Address Register. . . . . . 790
34.4.5.4.1 The ADDR field . . . . . . . . . . . . . . . . . . . . . . 791
34.4.5.5 MPU Region Attribute and Size Register. . . 791
34.4.5.5.1 SIZE field values . . . . . . . . . . . . . . . . . . . . . 792