RM0444 Rev 5 105/1390
RM0444 Embedded Flash memory (FLASH)
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Bit 25 ERRIE: Error interrupt enable
This bit enables the interrupt generation upon setting the OPERR flag in the FLASH_SR
register.
0: Disable
1: Enable
Bit 24 EOPIE: End-of-operation interrupt enable
This bit enables the interrupt generation upon setting the EOP flag in the FLASH_SR register.
0: Disable
1: Enable
Bits 23:19 Reserved, must be kept at reset value.
Bit 18 FSTPG: Fast programming enable
0: Disable
1: Enable
Bit 17 OPTSTRT: Start of modification of option bytes
This bit triggers an options operation when set.
This bit is set only by software, and is cleared when the BSY1 bit is cleared in FLASH_SR.
Bit 16 STRT: Start erase operation
This bit triggers an erase operation when set.
This bit is possible to set only by software and to clear only by hardware. The hardware
clears it when one of BSY1 and BSY2 flags in the FLASH_SR register transits to zero.
Bit 15 MER2: Mass erase, Bank 2
When set, this bit triggers the mass erase of Bank 2 (all user pages).
Bits 14 Reserved, must be kept at reset value.
Bit 13 BKER: Bank selection for erase operation
This bit selects the target of erase operation (Bank 1 or Bank 2).
0: Bank 1
1: Bank 2
The bit has no effect on the single-bank devices.
Bits 12:3 PNB[9:0]: Page number selection
These bits select the page to erase:
0x00: page 0
0x01: page 1
...
0x17F: page 383
Note: Values corresponding to addresses outside the Main memory are not allowed.
Bit 2 MER1: Mass erase (Bank 1)
When set, this bit triggers the mass erase, that is, all user pages (of Bank 1 for dual-bank
devices).
Bit 1 PER: Page erase enable
0: Disable
1: Enable
Bit 0 PG: Flash memory programming enable
0: Disable
1: Enable
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