System configuration controller (SYSCFG) RM0444
262/1390 RM0444 Rev 5
8.1.23 SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20)
Address offset: 0xD0
System reset value: 0x0000 0000
8.1.24 SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21)
Address offset: 0xD4
System reset value: 0x0000 0000
8.1.25 SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22)
Address offset: 0xD8
System reset value: 0x0000 0000
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 TIM14: Timer 14 interrupt request pending
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
TIM15
(1)
r
1. Only significant on devices integrating TIM15, otherwise reserved. Refer to Section 1.4: Availability of peripherals.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 TIM15: Timer 15 interrupt request pending
(1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
FDCAN
2_IT0
(1)
FDCAN
1_IT0
(1)
TIM16
rr r
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
Bits 31:1 Reserved, must be kept at reset value.
Bit 2 FDCAN2_IT0: FDCAN2 interrupt request pending
(1)
Bit 1 FDCAN1_IT0: FDCAN1 interrupt request pending
(1)
Bit 0 TIM16: Timer 16 interrupt request pending
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