Reset and clock control (RCC) RM0444
196/1390 RM0444 Rev 5
5.4.13 I/O port clock enable register (RCC_IOPENR)
Address: 0x34
Reset value: 0x0000 0000
Bit 11 TIM1RST: TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: SYSCFG, COMP and VREFBUF reset
Set and cleared by software.
0: No effect
1: Reset SYSCFG + COMP + VREFBUF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
GPIOF
EN
GPIOE
EN
(1)
GPIOD
EN
GPIOC
EN
GPIOB
EN
GPIOA
EN
rw rw rw rw rw rw
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 GPIOFEN: I/O port F clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
Bit 4 GPIOEEN: I/O port E clock enable
(1)
This bit is set and cleared by software.
0: Disable
1: Enable
Bit 3 GPIODEN: I/O port D clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
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