RM0444 Rev 5 133/1390
RM0444 Power control (PWR)
159
When SEVONPEND = 1 in the Cortex
®
-M0+ system control register: by enabling
an interrupt in the peripheral control register and optionally in the NVIC. When the
MCU resumes from WFE, the peripheral interrupt pending bit and when enabled
the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending
register) have to be cleared.
All NVIC interrupts wake the MCU up, even the disabled ones.
–Event
Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is
not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ
channel pending bit as the pending bits corresponding to the event line is not set.
It may be necessary to clear the interrupt flag in the peripheral.
The MCU exits Standby and Shutdown low-power modes upon an external reset (NRST
pin), an IWDG reset, a rising or falling edge on one of enabled WKUPx pins, or upon an
RTC event. See Figure 281: RTC block diagram.
After waking up from Standby or Shutdown mode, program execution restarts in the same
way as after a reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).
4.3.4 Sleep mode
I/O states in Sleep mode
In Sleep mode, all I/O pins keep the same state as in Run mode.
Entering Sleep mode
The MCU enters Sleep mode according to section Entering low-power modes, when the
SLEEPDEEP bit in the Cortex
®
-M0+ System Control register is clear.
Refer to Table 28: Sleep mode summary for details on how to enter Sleep mode.
Exiting Sleep mode
The MCU exits Sleep mode according to Exiting low-power modes.
Refer to Table 28: Sleep mode summary for more details on how to exit Sleep mode.
Table 28. Sleep mode summary
Characteristic Description
Mode entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex
®
-M0+ system control register.
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex
®
-M0+ system control register.