Basic timers (TIM6/TIM7) RM0444
708/1390 RM0444 Rev 5
Figure 219. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)
23.3.3 UIF bit remapping
The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update
Interrupt Flag UIF into the timer counter register’s bit 31 (TIMxCNT[31]). This allows to
atomically read both the counter value and a potential roll-over condition signaled by the
UIFCPY flag. In particular cases, it can ease the calculations by avoiding race conditions
caused for instance by a processing shared between a background task (counter reading)
and an interrupt (Update Interrupt).
There is no latency between the assertions of the UIF and UIFCPY flags.
23.3.4 Clock source
The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 220 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.
MS31083V2
F5
36
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag
(UIF)
00
02
03 04 05
06
07F1
F2
F3 F4
F5F0
01
CEN
Auto-reload preload
register
Write a new value in TIMx_ARR
Auto-reload shadow
register
F5
36
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