ST STM32G0 1 Series - Peripherals Independent Clock Configuration Register (RCC_CCIPR)

RM0444 Rev 5 209/1390
RM0444 Reset and clock control (RCC)
220
5.4.21 Peripherals independent clock configuration register (RCC_CCIPR)
Address: 0x54
Reset value: 0x0000 0000
Bit 18 TIM17SMEN: TIM16 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 17 TIM16SMEN: TIM16 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 16 TIM15SMEN: TIM15 timer clock enable during Sleep mode
(1)
Set and cleared by software.
0: Disable
1: Enable
Bit 15 TIM14SMEN: TIM14 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 14 USART1SMEN: USART1 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1SMEN: SPI1 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 11 TIM1SMEN: TIM1 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGSMEN: SYSCFG, COMP and VREFBUF clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable