ST STM32G0 1 Series User Manual

RM0444 Rev 5 605/1390
RM0444 Advanced-control timer (TIM1)
624
21.4.12 TIM1 counter (TIM1_CNT)
Address offset: 0x24
Reset value: 0x0000 0000
21.4.13 TIM1 prescaler (TIM1_PSC)
Address offset: 0x28
Reset value: 0x0000
21.4.14 TIM1 auto-reload register (TIM1_ARR)
Address offset: 0x2C
Reset value: 0xFFFF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UIF
CPY
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
r
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CNT[15:0]
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Bit 31 UIFCPY: UIF copy
This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in
the TIMxCR1 is reset, bit 31 is reserved and read at 0.
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
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PSC[15:0]
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Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (CK_CNT) is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).
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ARR[15:0]
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Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 21.3.1: Time-base unit on page 526 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English