ST STM32G0 1 Series User Manual

General-purpose timers (TIM15/TIM16/TIM17) RM0444
756/1390 RM0444 Rev 5
Figure 252. Output stage of capture/compare channel (channel 1)
Figure 253. Output stage of capture/compare channel (channel 2 for TIM15)
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
25.4.6 Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
MSv65226V1
OC1M[3:0]
Output
mode
controller
CNT>CCR1
CNT=CCR1
TIMx_CCMR1
OC1REF
Dead-time
generator
OC1_DT
OC1N_DT
DTG[7:0]
TIMx_BDTR
‘0’
‘0’
CC1E
TIMx_CCER
CC1NE
0
1
CC1P
TIM1_CCER
0
1
CC1NP
TIMx_CCER
OC1
Output
enable
circuit
OC1N
CC1E
TIMx_CCER
CC1NE
OSSI
TIMx_BDTR
MOE OSSR
0x
10
11
11
01
x0
Output
selector
OC2REF
OC1REFC
To the master mode
controller
Output
enable
circuit
OIS1 OIS1N
TIMx_CR2
MSv65242V1
Output
mode
controller
CNT > CCR2
CNT = CCR2
TIMx_CCMR1
0
1
CC2P
TIMx_CCER
Output
enable
circuit
OC2
CC2E
TIMx_CCER
To the master
mode controller
OC2REF
Output
selector
OC1REF
0
1
CC2E
TIMx_CCER
OC2REFC
OC2M[3:0]
‘0’
OIS2
TIMx_CR2

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English