RM0444 Rev 5 265/1390
RM0444 System configuration controller (SYSCFG)
269
8.1.31 SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28)
Address offset: 0xF0
System reset value: 0x0000 0000
8.1.32 SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29)
Address offset: 0xF4
System reset value: 0x0000 0000
8.1.33 SYSCFG interrupt line 30 status register (SYSCFG_ITLINE30)
Address offset: 0xF8
System reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LPUAR
T2
(1)
USART2
rr
1. Only significant on devices integrating LPUART2, otherwise reserved. Refer to Section 1.4: Availability of peripherals.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 LPUART2: LPUART2 interrupt request pending
(1)
Bit 0 USART2: USART2 interrupt request pending (EXTI line 26)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
USART6
(1)
USART5
(1)
LPUART1
USART4
(1)
USART3
(1)
rr r rr
1. Only significant on devices integrating the corresponding peripheral, otherwise reserved. Refer to Section 1.4: Availability
of peripherals.
Bits 31:5 Reserved, must be kept at reset value.
Bit 4 USART6: USART6 interrupt request pending
(1)
Bit 3 USART5: USART5 interrupt request pending
(1)
Bit 2 LPUART1: LPUART1 interrupt request pending (EXTI line 28)
Bit 1 USART4: USART4 interrupt request pending
(1)
Bit 0 USART3: USART3 interrupt request pending (EXTI line 28)
(1)
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