RM0444 Rev 5 1253/1390
RM0444 FD controller area network (FDCAN)
1261
36.4.29 FDCAN Tx buffer add request register (FDCAN_TXBAR)
Address offset: 0x00CC
Reset value: 0x0000 0000
Note: If an add request is applied for a Tx buffer with pending transmission request
(corresponding TXBRP bit already set), the request is ignored.
36.4.30 FDCAN Tx buffer cancellation request register (FDCAN_TXBCR)
Address offset: 0x00D0
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AR[2:0]
rw rw rw
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 AR[2:0]: Add request
Each Tx buffer has its own add request bit. Writing a 1 sets the corresponding add request
bit; writing a 0 has no impact. This enables the Host to set transmission requests for multiple
Tx buffers with one write to TXBAR. When no Tx scan is running, the bits are reset
immediately, else the bits remain set until the Tx scan process has completed.
0: No transmission request added
1: Transmission requested added.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CR[2:0]
rw rw rw
Bits 31:3 Reserved, must be kept at reset value.
Bits 2:0 CR[2:0]: Cancellation request
Each Tx buffer has its own cancellation request bit. Writing a 1 sets the corresponding CR bit;
writing a 0 has no impact.
This enables the Host to set cancellation requests for multiple Tx buffers with one write to
TXBCR. The bits remain set until the corresponding TXBRP bit is reset.
0: No cancellation pending
1: Cancellation pending
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