ST STM32G0 1 Series

Direct memory access controller (DMA) RM0444
278/1390 RM0444 Rev 5
10.3 DMA implementation
10.3.1 DMA
The devices incorporate one or two DMA controller instances. The following implementation
table shows the number of DMA channels for either instance. A dash indicates that the
instance is not implemented.
10.3.2 DMA request mapping
The DMA controller is connected to DMA requests from the AHB/APB peripherals through
the DMAMUX peripheral.
For the mapping of the different requests, refer to the Section 11.3: DMAMUX
implementation.
10.4 DMA functional description
10.4.1 DMA block diagram
Table 46. DMA implementation
Number of channels
STM32G031xx
STM32G041xx
STM32G051xx
STM32G061xx
STM32G071xx
STM32G081xx
STM32G0B1xx
STM32G0C1xx
DMA1 5 7 7
DMA2 - - 5