Power control (PWR) RM0444
122/1390 RM0444 Rev 5
VBAT battery charging
When V
DD
is present, it is possible to charge the external battery on VBAT through an
internal resistance.
The VBAT charging is done either through a 5 kΩ resistor or through a 1.55 kΩ resistor
depending on the VBRS bit value in the PWR_CR4 register.
The battery charging is enabled by setting VBE bit in the PWR_CR4 register. It is
automatically disabled in VBAT mode.
4.1.3 Voltage regulator
Two embedded linear voltage regulators supply all the digital circuitries, except for the
Standby circuitry and the RTC domain. The main regulator output voltage (V
CORE
) can be
programmed by software to two different power ranges (Range 1 and Range 2) in order to
optimize the consumption depending on the system maximum operating frequency (refer to
Section 5.2.8: Clock source frequency versus voltage scaling and to Section 3.3.4: FLASH
read access latency.
The voltage regulators are always enabled after a reset. Depending on the user application
modes, the V
CORE
supply is provided either by the main regulator (MR) or by the low-power
regulator (LPR).
• In Run, Sleep and Stop 0 modes, both regulators are enabled and the main regulator
(MR) supplies full power to the V
CORE
domain (core, memories and digital peripherals).
• In Low-power run and Low-power sleep modes, the main regulator is off and the low-
power regulator (LPR) supplies low-power to the V
CORE
domain, preserving the
contents of the registers and SRAM.
• In Stop 1 mode, the main regulator is off and the low-power regulator (LPR) supplies
low-power to the V
CORE
domain, preserving the contents of the registers and SRAM.
• In Standby mode with SRAM content preserved (RRS bit is set in the PWR_CR3
register), the main regulator (MR) is off and the low-power regulator (LPR) provides the
supply to SRAM only. The core and digital peripherals (except Standby circuitry and
RTC domain) are powered off.
• In Standby mode, both regulators are powered off. The contents of the registers and
SRAM is lost except for the Standby circuitry and the RTC domain.
• In Shutdown mode, both regulators are powered off. When exiting Shutdown mode, a
power-on reset is generated. Consequently, the contents of the registers and SRAM is
lost, except for the RTC domain.
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