ST STM32G0 1 Series - Page 121

RM0444 Rev 5 121/1390
RM0444 Power control (PWR)
159
Warning: During t
RSTTEMPO
(temporization at V
DD
startup) or after a PDR
has been detected, the power switch between V
BAT
and V
DD
remains connected to V
BAT
.
During the startup phase, if V
DD
is established in less than
t
RSTTEMPO
(refer to the datasheet for the value of t
RSTTEMPO
)
and V
DD
> V
BAT
+ 0.6 V, a current may be injected into V
BAT
through an internal diode connected between V
DD
and the
power switch (V
BAT
).
If the power supply/battery connected to the VBAT pin cannot
support this current injection, it is recommended to connect
an external low-drop diode between this power supply and
the VBAT pin.
If no external battery is used in the user application, it is recommended to connect VBAT pin
externally to VDD/VDDA pin with a 100 nF external ceramic decoupling capacitor.
When the RTC domain is supplied by V
DD
(power switch connected to V
DD
), all the related
pin functions are available:
When the RTC domain is supplied by V
BAT
(power switch connected to V
BAT
because V
DD
is not present), only the following functions are available:
• PC13, PC14 and PC15 can be controlled only by RTC, TAMP or LSE (refer to
Section 30.3: RTC functional description)
• RTC_OUT1 function on PC13
• RTC_TS function on PC13 or PA4
• TAMP_IN1 function on PC13 or PA4 and TAMP_IN2 function on PA0
Note: Due to the fact that the power switch can transfer only a limited amount of current (3 mA),
the use of GPIO PC13 to PC15 in output mode is restricted: the speed has to be limited to
2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source
(e.g. to drive a LED).
RTC domain access
After a system reset, the RTC domain (RTC registers and backup registers) is protected
against possible unwanted write accesses. To enable access to the RTC domain, proceed
as follows:
1. Enable the power interface clock by setting the PWREN bits of the APB peripheral
clock enable register 1 (RCC_APBENR1).
2. Set the DBP bit of the Power control register 1 (PWR_CR1) to enable access to the
RTC domain.
3. Select the RTC clock source in the RTC domain control register (RCC_BDCR).
4. Enable the RTC clock by setting the RTCEN bit in the RTC domain control register
(RCC_BDCR).