ST STM32G0 1 Series - FDCAN Registers; FDCAN Core Release Register (FDCAN_CREL); FDCAN Endian Register (FDCAN_ENDN)

RM0444 Rev 5 1227/1390
RM0444 FD controller area network (FDCAN)
1261
36.4 FDCAN registers
36.4.1 FDCAN core release register (FDCAN_CREL)
Address offset: 0x0000
Reset value: 0x3214 1218
36.4.2 FDCAN endian register (FDCAN_ENDN)
Address offset: 0x0004
Reset value: 0x8765 4321
Note: The register read must give the reset value to ensure no endiandess issue.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REL[3:0] STEP[3:0] SUBSTEP[3:0] YEAR[3:0]
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1514131211109876543210
MON[7:0] DAY[7:0]
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Bits 31:28 REL[3:0]: 3
Bits 27:24 STEP[3:0]: 2
Bits 23:20 SUBSTEP[3:0]: 1
Bits 19:16 YEAR[3:0]: 4
Bits 15:8 MON[7:0]: 12
Bits 7:0 DAY[7:0]: 18
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ETV[31:16]
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1514131211109876543210
ETV[15:0]
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Bits 31:0 ETV[31:0]: Endianness test value
The endianness test value is 0x8765 4321.