RM0444 Rev 5 143/1390
RM0444 Power control (PWR)
159
4.4 PWR registers
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
4.4.1 Power control register 1 (PWR_CR1)
Address offset: 0x00
Reset value: 0x0000 0208. This register is reset after wakeup from Standby mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. LPR Res. Res. Res. VOS[1:0] DBP Res. Res.
FPD_
LPSLP
FPD_
LPRUN
FPD_
STOP
LPMS[2:0]
rw rw rw rw rw rw rw rw rw rw
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 LPR: Low-power run
When this bit is set, the regulator is switched from main mode (MR) to low-power mode
(LPR).
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:9 VOS: Voltage scaling range selection
00: Cannot be written (forbidden by hardware)
01: Range 1
10: Range 2
11: Cannot be written (forbidden by hardware)
Bit 8 DBP: Disable RTC domain write protection
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and backup registers disabled
1: Access to RTC and backup registers enabled
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 FPD_LPSLP: Flash memory powered down during Low-power sleep mode
This bit determines whether the Flash memory is put in power-down mode or remains in idle
mode when the device enters Low-power sleep mode.
0: Flash memory idle
1: Flash memory powered down
To Next Page
Loading...
Need help?
General
