General-purpose timers (TIM2/TIM3/TIM4) RM0444
666/1390 RM0444 Rev 5
Figure 207. Gating TIM2 with Enable of TIM3
Using one timer to start another timer
In this example, we set the enable of Timer 2 with the update event of Timer 3. Refer to
Figure 204 for connections. Timer 2 starts counting from its current value (which can be
non-zero) on the divided internal clock as soon as the update event is generated by Timer 1.
When Timer 2 receives the trigger signal its CEN bit is automatically set and the counter
counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock
frequencies are divided by 3 by the prescaler compared to CK_INT (f
CK_CNT
= f
CK_INT
/3).
1. Configure TIM3 master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM3_CR2 register).
2. Configure the TIM3 period (TIM3_ARR registers).
3. Configure TIM2 to get the input trigger from TIM3 (TS=00010 in the TIM2_SMCR
register).
4. Configure TIM2 in trigger mode (SMS=110 in TIM2_SMCR register).
5. Start TIM3 by writing ‘1 in the CEN bit (TIM3_CR1 register).
Figure 208. Triggering TIM2 with update of TIM3
MS33120V1
CK_INT
75 00
E7
TIM3-CNT_INIT
TIM3-CNT
AB
TIM2-CNT
TIM2-CNT_INIT
Write TIF = 0
01 02
E9E800
TIM3-CEN=CNT_EN
TIM2-write CNT
TIM2-TIF
MS33121V1
CK_INT
TIM2-CNT
FDTIM3-CNT
Write TIF = 0
TIM2-CEN=CNT_EN
TIM2-TIF
FE FF 00 01 02
46 47 4845
TIM3-UEV
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