ST STM32G0 1 Series User Manual

Reset and clock control (RCC) RM0444
166/1390 RM0444 Rev 5
Figure 10. Clock tree
1. Only applies to STM32G071xx and STM32G081xx and to STM32G0B1xx and STM32G0C1xx.
2. Only applies to STM32G0B1xx and STM32G0C1xx.
PLL
VCO
/N
x
f
VCO
SYSCLK
MCO
LSCO
to RNG
async clock to ADC
to IWDG
to RTC
to PWR
HCLK
to AHB bus, core, memory and DMA
FCLK Cortex free-running clock
to Cortex system timer
to APB peripherals
PCLK
to I2S1
LSE
HSI16
SYSCLK
to USART1
LPUART1
LPUART2
to I2C1
to LPTIM1/2
I2S_CKIN
to TIM2/3/4/6/7/14/16/17
OSC32_OUT
OSC32_IN
HSI16
HSE
HSI16
LSI
LSE
HSE
SYSCLK
HSE
HSISYS
HSI16
SYSCLK
LSI
LSE
HSI16
HSI16 RC
16 MHz
OSC_OUT
OSC_IN
LSI RC
32 kHz
PLLRCLK
PLLQCLK
PLLPCLK
to CEC
LSE
HSI16
HSI16
HSI16
HSI16
to UCPD1/2
(1)
HSI16
to TIM1
/ 488
/1,2,4,8
LSE
LSI
/32
AHB
PRESC
/ 1,2,..512
/ 1...1024
HSE OSC
4-48 MHz
Clock
detector
APB
PRESC
/ 1,2,4,8,16
/ 8
x1, x2
/1…128
LSI
HSE
LSE
HSI16
PLLQCLK
(2)
PLLRCLK
TIMPCLK
PLLQCLK
PLLPCLK
SYSCLK
I2S_CKIN
PLLPCLK
SYSCLK
PLLQCLK
SYSCLK
BOLD: clock origin
LSE
LSI
LSE
LSI
HSE
TIMPCLK
PCLK
PCLK
PCLK
HSISYS
HCLK8
f
PLLIN
/ R
/ Q
/ P
/M
f
PLLR
f
PLLQ
f
PLLP
LPTIMx_IN
LSE OSC
32.768 kHz
Clock
detector
/ 8
TIM15
(1)
USART2
(1)
HSI48 RC
48 MHz
CRS
HSI48
I2C2
I2S2
HSE
PLLQCLK
HSI48
to USB
(2)
HSE
PLLQCLK
PCLK
to FDCAN
(2)
USART3
HSI48
(2)
PLLRCLK
PLLPCLK
(2)
RTCCLK
(2)
RTC WAKEUP
(2)
MCO2
(2)
/ 1...1024
RTCCLK
RTC WAKEUP
from RTC
HSI48

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English