ST STM32G0 1 Series - Figure 225. Counter Timing Diagram, Internal Clock Divided by 2; Figure 226. Counter Timing Diagram, Internal Clock Divided by 4

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General-purpose timers (TIM14) RM0444

720/1390 RM0444 Rev 5

Figure 225. Counter timing diagram, internal clock divided by 2

Figure 226. Counter timing diagram, internal clock divided by 4

MS31079V2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register

Update event (UEV)

Counter overflow

Update interrupt flag

(UIF)

0034

0035

0036

0000

0001

0002

0003