Embedded Flash memory (FLASH) RM0444
68/1390 RM0444 Rev 5
3 Embedded Flash memory (FLASH)
3.1 FLASH Introduction
The Flash memory interface manages CPU (Cortex
®
-M0+) AHB to the Flash memory. It
implements erase and program Flash memory operations, read and write protection, and
security mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
3.2 FLASH main features
• Up to 512 Kbytes of Flash memory (Main memory):
– up to 64 Kbytes for STM32G031xx and STM32G041xx / STM32G051xx and
STM32G061xx
– up to 128 Kbytes for STM32G071xx and STM32G081xx
– up to 512 Kbytes for STM32G0B1xx and STM32G0C1xx
• Memory organization:
– 1 bank (products with up to 128 Kbytes of Flash memory)
– 2 banks (products with more than 128 Kbytes of Flash memory)
– Page size: 2 Kbytes
– Subpage size: 512 bytes
• 72-bit wide data read (64 bits plus 8 ECC bits)
• 72-bit wide data write (64 bits plus 8 ECC bits)
• Page erase (2 Kbytes), bank (single-bank) erase, and mass (all-bank) erase
Flash memory interface features:
• Flash memory read operations
• Flash memory program/erase operations
• Read protection activated by option (RDP)
• Two write protection areas per bank, selected by option (WRP)
• Two proprietary code read protection areas per bank, selected by option (PCROP)
• Securable memory area
• Flash memory empty check
• Prefetch buffer
• CPU instruction cache: two cache lines of 64 bits (16 bytes RAM)
• Error code correction (ECC): eight bits for 64 bits
• Option byte loader
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