RM0444 Rev 5 183/1390
RM0444 Reset and clock control (RCC)
220
5.4.4 PLL configuration register (RCC_PLLCFGR)
Address offset: 0x0C
Reset value: 0x0000 1000
This register configures the PLL clock outputs according to the formulas:
• f
VCO
= f
PLLIN
× (N / M)
• f
PLLP
= f
VCO
/ P
• f
PLLQ
= f
VCO
/ Q
• f
PLLR
= f
VCO
/ R
Bits 11:8 HPRE[3:0]: AHB prescaler
This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of
SYSCLK clock as follows:
0xxx: 1
1000: 2
1001: 4
1010: 8
1011: 16
1100: 64
1101: 128
1110: 256
1111: 512
Caution: Depending on the device voltage range, the software has to set correctly these bits to
ensure that the system frequency does not exceed the maximum allowed frequency
(for more details, refer to Section 4.1.4: Dynamic voltage scaling management). After
a write operation to these bits and before decreasing the voltage range, this register
must be read to be sure that the new value has been taken into account.
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:3 SWS[2:0]: System clock switch status
This bitfield is controlled by hardware to indicate the clock source used as system clock:
000: HSISYS
001: HSE
010: PLLRCLK
011: LSI
100: LSE
Others: Reserved
Bits 2:0 SW[2:0]: System clock switch
This bitfield is controlled by software and hardware. The bitfield selects the clock for
SYSCLK as follows:
000: HSISYS
001: HSE
010: PLLRCLK
011: LSI
100: LSE
Others: Reserved
The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop,
Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator
failure is detected.
To Next Page
Loading...
Need help?
General
