Digital-to-analog converter (DAC) RM0444
410/1390 RM0444 Rev 5
16.4.5 DAC conversion
The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must
be performed by loading the DAC_DHRx register (write operation to DAC_DHR8Rx,
DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12RD or DAC_DHR12LD).
Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx
register after one dac_pclk clock cycle, if no hardware trigger is selected (TENx bit in
DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in
DAC_CR register is set) and a trigger occurs, the transfer is performed three dac_pclk clock
cycles after the trigger signal.
When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage
becomes available after a time t
SETTLING
that depends on the power supply voltage and the
analog output load.
Figure 62. Timing diagram for conversion with trigger disabled TEN = 0
16.4.6 DAC output voltage
Digital inputs are converted to output voltages on a linear conversion between 0 and V
REF+
.
The analog output voltages on each DAC channel pin are determined by the following
equation:
16.4.7 DAC trigger selection
If the TENx control bit is set, the conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSEL
x[3:0] control bits determine which out of 16 pos-
sible events triggers the conversion as shown in TSELx[3:0] bits of the DAC_CR register.
These events can be either the software trigger or hardware triggers. Refer to the intercon
-
nection table in Section 16.4.2: DAC pins and internal signals.
Each time a DAC interface detects a rising edge on the selected trigger source (refer to the
table below), the last data stored into the DAC_DHRx register are transferred into the
DAC_DORx register. The DAC_DORx register is updated three dac_pclk cycles after the
trigger occurs.
MSv45319V2
Bus clock
0x1AC
0x1AC
tSETTLING
DHR
DOR
Output voltage available on
DAC_OUT pin
DACoutput V
REF
DOR
4096
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