RM0444
66/1391 RM0444 Rev 5
The SRAM can be accessed by bytes, half-words (16 bits) or full words (32 bits), at
maximum system clock frequency without wait state and thus by both CPU and DMA.
Parity check
The user can enable the parity check using the option bit RAM_PARITY_CHECK in the user
option byte (refer to Section 3.4: FLASH option bytes).
The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in
order to increase memory robustness, as required for instance by Class B or SIL norms.
The parity bits are computed and stored when writing into the SRAM. Then, they are
automatically checked when reading. If one bit fails, an NMI is generated. The same error
can also be linked to the BRK_IN Break input of TIM1/15/16/17, with the
SRAM_PARITY_LOCK control bit in the SYSCFG configuration register 2
(SYSCFG_CFGR2). The SRAM Parity Error flag (SRAM_PEF) is available in the SYSCFG
configuration register 2 (SYSCFG_CFGR2).
Note: When enabling the SRAM parity check, it is advised to initialize by software the whole
SRAM at the beginning of the code, to avoid getting parity errors when reading non-
initialized locations.
2.4 Flash memory overview
The Flash memory is composed of two distinct physical areas:
• The main Flash memory block. It contains the application program and user data if
necessary.
• The information block. It is composed of three parts:
– Option bytes for hardware and memory protection user configuration.
– System memory which contains the proprietary boot loader code.
– OTP (one-time programmable) area
Refer to Section 3: Embedded Flash memory (FLASH) for more details.
The Flash interface implements instruction access and data access based on the AHB
protocol. It implements the prefetch buffer that speeds up CPU code execution. It also
implements the logic necessary to carry out the Flash memory operations (Program/Erase)
controlled through the Flash registers.
2.5 Boot configuration
In the STM32G0x1, three different boot modes can be selected through the BOOT0 pin,
BOOT_LOCK bit in FLASH_SECR register, and boot configuration bits nBOOT1,
BOOT_SEL and nBOOT0 in the User option byte, as shown in the following table.
Table 8. Boot modes
Boot mode configuration
Selected boot area
BOOT_
LOCK bit
nBOOT1
bit
BOOT0
pin
nBOOT_SEL
bit
nBOOT0
bit
0 x 0 0 x Main Flash memory
0 1 1 0 x System memory
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