General-purpose timers (TIM15/TIM16/TIM17) RM0444
798/1390 RM0444 Rev 5
25.5.15 TIM15 capture/compare register 2 (TIM15_CCR2)
Address offset: 0x38
Reset value: 0x0000
25.5.16 TIM15 break and dead-time register (TIM15_BDTR)
Address offset: 0x44
Reset value: 0x0000 0000
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CCR2[15:0]
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Bits 15:0 CCR2[15:0]: Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. BKBID Res.
BK
DSRM
Res. Res. Res. Res. Res. Res. BKF[3:0]
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MOE AOE BKP BKE OSSR OSSI LOCK[1:0] DTG[7:0]
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Note: As the BKBID, BKDSRM, BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may
be write-locked depending on the LOCK configuration, it may be necessary to configure all
of them during the first write access to the TIMx_BDTR register.
Bits 31:29 Reserved, must be kept at reset value.
Bit 28 BKBID: Break Bidirectional
0: Break input BRK in input mode
1: Break input BRK in bidirectional mode
In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input
mode and in open drain output mode. Any active break event asserts a low logic level on the
Break input to indicate an internal break event to external devices.
Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits
in TIMx_BDTR register).
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
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