RM0444 Rev 5 115/1390
RM0444 Embedded Flash memory (FLASH)
118
3.7.18 FLASH WRP2 area B address register (FLASH_WRP2BR)
Address offset: 0x050
Reset value: 0b0000 0000 0XXX XXXX 0000 0000 0XXX XXXX (The option bits are loaded
with values from Flash memory at power-on reset release.)
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access.
3.7.19 FLASH PCROP2 area B start address register
(FLASH_PCROP2BSR)
Address offset: 0x054
Reset value: 0b0000 0000 0000 0000 0000 000X XXXX XXXX (The option bits are loaded
with values from Flash memory at power-on reset release.)
Access: no wait state when no Flash memory operation is on going, word, half-word access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2B_END[6:0]
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2B_STRT[6:0]
rw rw rw rw rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:16 WRP2B_END[6:0]: WRP area B end offset, Bank 2
This bitfield contains the offset of the last page of the WRP area B in Bank 2.
(1)
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP2B_STRT[6:0]: WRP area B start offset, Bank 2
This bitfield contains the offset of the first page of the WRP area B in Bank 2.
(1)
1. The number of effective bits depends on the size of Flash memory in the device.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8 765432 1 0
Res. Res. Res. Res. Res. Res. Res. PCROP2B_STRT[8:0]
rw rw rw rw rw rw rw rw rw
Bits 31:9 Reserved, must be kept cleared
Bits 8:0 PCROP2B_STRT[8:0]: PCROP2B area start offset, Bank 2
Contains the offset of the first subpage of the PCROP2B area in Bank 2.
(1)
1. The number of effective bits depends on the size of Flash memory in the device.
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