General-purpose timers (TIM15/TIM16/TIM17) RM0444
780/1390 RM0444 Rev 5
25.4.22 Timer synchronization (TIM15)
The TIMx timers are linked together internally for timer synchronization or chaining. Refer to
Section 22.3.19: Timer synchronization for details.
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2
signals must be enabled prior to receive events from the master timer, and the clock
frequency (prescaler) must not be changed on-the-fly while triggers are received from the
master timer.
25.4.23 Using timer output as trigger for other timers (TIM16/TIM17)
The timers with one channel only do not feature a master mode. However, the OC1 output
signal can be used to trigger some other timers (including timers described in other sections
of this document). Check the “TIMx internal trigger connection” table of any TIMx_SMCR
register on the device to identify which timers can be targeted as slave.
The OC1 signal pulse width must be programmed to be at least 2 clock cycles of the
destination timer, to make sure the slave timer will detect the trigger.
For instance, if the destination's timer CK_INT clock is 4 times slower than the source timer,
the OC1 pulse width must be 8 clock cycles.
25.4.24 Debug mode
When the microcontroller enters debug mode (Cortex
®
-M0+ core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to Section 40.9.2: Debug support for timers,
watchdog and I
2
C.
For safety purposes, when the counter is stopped (DBG_TIMx_STOP = 1), the outputs are
disabled (as if the MOE bit was reset). The outputs can either be forced to an inactive state
(OSSI bit = 1), or have their control taken over by the GPIO controller (OSSI bit = 0) to force
them to Hi-Z.
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