System configuration controller (SYSCFG) RM0444
264/1390 RM0444 Rev 5
8.1.28 SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25)
Address offset: 0xE4
System reset value: 0x0000 0000
8.1.29 SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26)
Address offset: 0xE8
System reset value: 0x0000 0000
8.1.30 SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27)
Address offset: 0xEC
System reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SPI1
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SPI1: SPI1 interrupt request pending
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SPI3
(1)
SPI2
rr
1. Only significant on devices integrating SPI3, otherwise reserved. Refer to Section 1.4: Availability of peripherals.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 SPI3: SPI3 interrupt request pending
(1)
Bit 0 SPI2: SPI2 interrupt request pending
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. USART1
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 USART1: USART1 interrupt request pending, combined with EXTI line 25
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