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RM0444 Rev 5 693/1390

RM0444 General-purpose timers (TIM2/TIM3/TIM4)

701

22.4.23 TIM3 option register 1 (TIM3_OR1)

Address offset: 0x50

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

OCREF_CLR

[1:0]

rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bits 1:0 OCREF_CLR[1:0]: Ocref_clr source selection

This bit selects the ocref_clr input source.

00: COMP1 output is connected to the OCREF_CLR input

01: COMP2 output is connected to the OCREF_CLR input

10: COMP3

(1)

output is connected to the OCREF_CLR input

11: Reserved

1. COMP3 is available on STM32G0B1xx and STM32G0C1xx salestypes only.