System configuration controller (SYSCFG) RM0444
254/1390 RM0444 Rev 5
8.1.4 SYSCFG interrupt line 1 status register (SYSCFG_ITLINE1)
Address offset: 0x84
System reset value: 0x0000 0000
8.1.5 SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2)
Address offset: 0x88
System reset value: 0x0000 0000
8.1.6 SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3)
Address offset: 0x8C
System reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15141312111098765432 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
PVMOUT
(1)
PVDOUT
rr
1. Only significant on devices integrating V
DDIO2
monitor, otherwise reserved. Refer to Section 1.4: Availability of peripherals.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 PVMOUT: V
DDIO2
supply monitoring interrupt request pending (EXTI line 34).
Bit 0 PVDOUT: PVD supply monitoring interrupt request pending (EXTI line 16).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RTC TAMP
rr
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 RTC: RTC interrupt request pending (EXTI line 19)
Bit 0 TAMP: Tamper interrupt request pending (EXTI line 21)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
FLASH_
ECC
FLASH_
ITF
rr
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