ST STM32G0 1 Series - Timx Auto-Reload Register (Timx_Arr)(X = 2 to 4); Timx Capture;Compare Register 1 (Timx_Ccr1)(X = 2 to 4)

RM0444 Rev 5 689/1390
RM0444 General-purpose timers (TIM2/TIM3/TIM4)
701
22.4.15 TIMx auto-reload register (TIMx_ARR)(x = 2 to 4)
Address offset: 0x2C
Reset value: 0xFFFF FFFF
22.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 4)
Address offset: 0x34
Reset value: 0x0000 0000
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency CK_CNT is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).
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ARR[31:16]
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1514131211109876543210
ARR[15:0]
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Bits 31:16 ARR[31:16]: High auto-reload value (TIM2)
Bits 15:0 ARR[15:0]: Low Auto-reload value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 22.3.1: Time-base unit on page 627 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.
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CCR1[31:16]
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1514131211109876543210
CCR1[15:0]
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