RM0444 Rev 5 69/1390
RM0444 Embedded Flash memory (FLASH)
118
3.3 FLASH functional description
3.3.1 FLASH memory organization
The Flash memory is organized as 72-bit-wide memory cells (64 bits plus 8 ECC bits) that
can be used for storing both code and data constants.
The Flash memory is organized as follows:
• A Main memory block containing 128 pages of 2 Kbytes, each page with eight rows of
256 bytes.
• An Information block containing:
– System memory from which the CPU boots in System memory boot mode. The
area is reserved and contains the boot loader used to reprogram the Flash
memory through one of the following interfaces: USART1, USART2, I2C1, and
I2C2 (applies to all devices), USART3, SPI1, and SPI2 (applies to STM32G071xx
and STM32G081xx and to STM32G0B1xx and STM32G0C1xx), and through USB
(DFU) and FDCAN2 (applies to STM32G0B1xx and STM32G0C1xx). On the
manufacturing line, the devices are programmed and protected against spurious
write/erase operations. For further details, refer to the AN2606 available from
www.st.com.
– 1 Kbyte (128 double words) OTP (one-time programmable) for user data. The
OTP data cannot be erased and can be written only once. If only one bit is at 0,
the entire double word (64 bits) cannot be written anymore, even with the value
0x0000 0000 0000 0000.
The OTP area cannot be read when RDP level is 1 and boot source is not the
Main Flash memory area.
– Option bytes for user configuration.
The following tables show the mapping of the Flash memory into Information block and Main
memory area. The mapping for
Table 9. Flash memory organization for single-bank devices
Area Addresses
Size
(bytes)
16 Kbyte
devices
32 Kbyte
devices
64 Kbyte
devices
128 Kbyte
devices
Information
block
0x1FFF 7800 - 0x1FFF 787F 128 Option bytes
0x1FFF 7500 - 0x1FFF 77FF 768 Engineering bytes
0x1FFF 7000 - 0x1FFF 73FF 1 K OTP area
0x1FFF 2000 - 0x1FFF 6FFF 20 K -
System
memory
0x1FFF 0000 - 0x1FFF 1FFF 8 K System memory
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