RM0444 Rev 5 309/1390
RM0444 DMA request multiplexer (DMAMUX)
313
11.6.2 DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR)
Address offset: 0x080
Reset value: 0x0000 0000
11.6.3 DMAMUX request line multiplexer interrupt clear flag register
(DMAMUX_CFR)
Address offset: 0x084
Reset value: 0x0000 0000
Bit 7 Reserved, must be kept at reset value.
Bits 6:0 DMAREQ_ID[6:0]: DMA request identification
Selects the input DMA request. See the DMAMUX table about assignments of multiplexer
inputs to resources.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. SOF11 SOF10 SOF9 SOF8 SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0
r r rrrrrrrrrr
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 SOF[11:0]: Synchronization overrun event flag
The flag is set when a synchronization event occurs on a DMA request line multiplexer
channel x, while the DMA request counter value is lower than NBREQ.
The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res.
CSOF
11
CSOF
10
CSOF
9
CSOF
8
CSOF
7
CSOF
6
CSOF
5
CSOF
4
CSOF
3
CSOF
2
CSOF
1
CSOF
0
wwwwwwwwwwww
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 CSOF[11:0]: Clear synchronization overrun event flag
Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR
register.
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