ST STM32G0 1 Series - ADC Watchdog Threshold Register (ADC_AWD2 TR)

Analog-to-digital converter (ADC) RM0444
394/1390 RM0444 Rev 5
15.12.8 ADC watchdog threshold register (ADC_AWD2TR)
Address offset: 0x24
Reset value: 0x0FFF 0000
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to Section 15.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
ADC_AWDxTR) on page 369.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT1[11:0]: Analog watchdog 1 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 15.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
ADC_AWDxTR) on page 369.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. HT2[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. LT2[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 HT2[11:0]: Analog watchdog 2 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
Refer to Section 15.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
ADC_AWDxTR) on page 369.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT2[11:0]: Analog watchdog 2 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 15.7: Analog window watchdog (AWD1EN, AWD1SGL, AWD1CH, ADC_AWDxCR,
ADC_AWDxTR) on page 369.