ST STM32G0 1 Series User Manual

General-purpose timers (TIM14) RM0444
724/1390 RM0444 Rev 5
Figure 232. Capture/compare channel 1 main circuit
Figure 233. Output stage of capture/compare channel (channel 1)
1. Available on TIM12 only.
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
24.3.5 Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
MSv63030V1
CC1E
compare shadow register
Comparator
Capture/compare preload register
Counter
IC1PS
CC1S[0]
CC1S[1]
Capture
Input mode
CC1S[0]
CC1S[1]
Output mode
UEV
OC1PE
(from time
base unit)
Compare
transfer
APB Bus
16/32-bit
MCU-peripheral interface
TIMx_CCMR1
OC1PE
CNT>CCR1
CNT=CCR1
TIMx_EGR
CC1G
MSv45743V3
Output
mode
controller
CNT > CCR1
CNT = CCR1
Output
selector
OC2REF
(1)
OC1M[3:0]
TIMx_CCMR1
OC1REF OC1REFC
To the master mode
controller
0
1
‘0’
CC1E
TIM1_CCER
0
1
CC1P
TIM1_CCER
Output
enable
circuit
CC1E
TIM1_CCER
OC1

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English