ST STM32G0 1 Series User Manual

Clock recovery system (CRS) RM0444
226/1390 RM0444 Rev 5
6.7 CRS registers
Refer to Section 1.2 on page 53 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed only by words (32-bit).
6.7.1 CRS control register (CRS_CR)
Address offset: 0x00
Reset value: 0x0000 X000 (X=4 for products supporting 7-bit TRIM width, otherwise X=2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. TRIM[6:0]
SW
SYNC
AUTO
TRIMEN
CEN Res.
ESYNCI
E
ERRIE
SYNC
WARNIE
SYNC
OKIE
rw rw rw rw rw rw rw rt_w1 rw rw rw rw rw rw
Bits 31:15 Reserved, must be kept at reset value.
Bits 14:8 TRIM[6:0]: HSI48 oscillator smooth trimming
For product supporting the 7-bit TRIM width (see Section 6.3), the default value of the HSI48
oscillator smooth trimming is 64, which corresponds to the middle of the trimming interval.
For products supporting the 6-bit TRIM width (see Section 6.3) this bit is reserved, must be
kept at reset value.
Bit 7 SWSYNC: Generate software SYNC event
This bit is set by software in order to generate a software SYNC event. It is automatically
cleared by hardware.
0: No action
1: A software SYNC event is generated.
Bit 6 AUTOTRIMEN: Automatic trimming enable
This bit enables the automatic hardware adjustment of TRIM bits according to the measured
frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The
TRIM value can be adjusted by hardware by one or two steps at a time, depending on the
measured frequency error value. Refer to Section 6.4.4 for more details.
0: Automatic trimming disabled, TRIM bits can be adjusted by the user.
1: Automatic trimming enabled, TRIM bits are read-only and under hardware control.
Bit 5 CEN: Frequency error counter enable
This bit enables the oscillator clock for the frequency error counter.
0: Frequency error counter disabled
1: Frequency error counter enabled
When this bit is set, the CRS_CFGR register is write-protected and cannot be modified.
Bit 4 Reserved, must be kept at reset value.
Bit 3 ESYNCIE: Expected SYNC interrupt enable
0: Expected SYNC (ESYNCF) interrupt disabled
1: Expected SYNC (ESYNCF) interrupt enabled

ST STM32G0 1 Series Specifications

General

Brand	ST
Model	STM32G0 1 Series
Category	Microcontrollers
Language	English