General-purpose I/Os (GPIO) RM0444
240/1390 RM0444 Rev 5
7.3.13 Using the HSE or LSE oscillator pins as GPIOs
When the HSE or LSE oscillator is switched OFF (default state after reset), the related
oscillator pins can be used as normal GPIOs.
When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the
RCC_CSR register) the oscillator takes control of its associated pins and the GPIO
configuration of these pins has no effect.
When the oscillator is configured in a user external clock mode, only the OSC_IN or
OSC32_IN pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be
used as normal GPIO.
7.3.14 Using the GPIO pins in the RTC domain
The PC13/PC14/PC15 GPIO functionality is lost when the core supply domain is powered
off (when the device enters Standby mode). In this case, if their GPIO configuration is not
bypassed by the RTC configuration, these pins are set in an analog input mode.
For details about I/O control by the RTC, refer to Section 30.3: RTC functional description.
7.3.15 USB PD / Dead battery support
In the absence of V
DD
supply, the device using the Dead battery capability of the USB
Type-C standard provides an internal pull-down resistor R
d
on CC lines if the input level on
DBCC pins is high. This is to signal VBUS supply request.
To enable this feature, it is necessary to connect UCPD_DBCC1 to UCPD_CC1 and
UCPD_DBCC2 to UCPD_CC2. To disable the feature, it is necessary to connect
UCPD_DBCC1 and UCPD_DBCC2 to ground. Refer to Section 38: USB Type-C™ / USB
Power Delivery interface (UCPD) for more detail.
Note: The DBCC pads (GPIOs of FT_d type) present more leakage than standard GPIOs. Refer
to product datasheet for values.
In applications that do not use the UCPD peripheral, disable the internal pull-down resistor
R
d
at startup through the strobe bits in SYSCFG registers.
In applications that use the UCPD peripheral, first configure the peripheral then load the
configuration to the UCPD_CCx GPIOs through the strobe bits in SYSCFG registers.