RM0444 Rev 5 739/1390
RM0444 General-purpose timers (TIM14)
740
24.4.12 TIM14 timer input selection register (TIM14_TISEL)
Address offset: 0x68
Reset value: 0x0000
24.4.13 TIM14 register map
TIMx registers are mapped as 16-bit addressable registers as described in the tables below:
Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1SEL[3:0]
rw
Bits 15:4 Reserved, must be kept at reset value.
Bits 3:0 TI1SEL[3:0]: selects TI1[0] to TI1[15] input
0000: TIM14_CH1 input
0001: RTC CLK
0010: HSE/32
0011: MCO
0100: MCO2
(1)
Others: Reserved
1. Available on STM32G0B1xx and STM32G0C1xx salestypes only.
Table 124. TIM14 register map and reset values
Offset
Register
name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
TIMx_CR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
UIFREMA
Res.
CKD
[1:0]
ARPE
Res.
Res.
Res.
OPM
URS
UDIS
CEN
Reset value 0 000 000 0
0x04 to
0x08
Reserved Res.
0x0C
TIMx_DIER
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CC1IE
UIE
Reset value 00
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