RM0444 Rev 5 275/1390
RM0444 Interconnect matrix
276
More information is in:
• Section 15.2: ADC main features
• Section 15.3.8: Channel selection (CHSEL, SCANDIR, CHSELRMOD)
• Figure 15.9: Temperature sensor and internal reference voltage
• Figure 15.10: Battery voltage monitoring
Relevant power modes
These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power
modes.
9.3.9 From COMP1, COMP2, and COMP3 to TIM1, TIM2, TIM3, TIM4, TIM15,
TIM16, and TIM17
Purpose
COMP1, COMP2, and COMP3 comparator outputs can be connected to input capture or
TIMx_ETR inputs of TIM1, TIM2, TIM3, or TIM4.
The connection to ETR is described in Section 21.3.4: External trigger input.
COMP1, COMP2, and COMP3 comparator outputs can also act as TIMx_BKIN or
TIMx_BKIN2 break input signals for TIM1, TIM15, TIM16, and TIM17, through selecting
GPIO alternate function using open drain connection of I/O. See Section 21.3.17:
Bidirectional break inputs.
The possible connections are given in:
• Section 21.4.23: TIM1 option register 1 (TIM1_OR1)
• Section 21.4.28: TIM1 Alternate function register 2 (TIM1_AF2)
• Section 22.4.22: TIM2 option register 1 (TIM2_OR1)
• Section 25.3: TIM16/TIM17 main features
Relevant power modes
These interconnections operate in Run, Sleep, Low-power run, and Low-power sleep power
modes.
9.3.10 From system errors to TIM1, TIM2, TIM3, TIM4, TIM15, TIM16,
and TIM17
Purpose
CSS, CPU hardfault, RAM parity error, FLASH ECC double error detection, PVD can
generate system errors in the form of timer break toward TIM1, TIM2, TIM3, TIM4, TIM15,
TIM16, and TIM17.
The purpose of the break function is to protect power switches driven by PWM signals from
the timers.
To Next Page
Loading...
Need help?
General
