RM0444 Rev 5 173/1390
RM0444 Reset and clock control (RCC)
220
The LSE clock is in the RTC domain, whereas the HSE and LSI clocks are not.
Consequently:
• If LSE is selected as RTC clock:
– The RTC continues to work even if the V
DD
supply is switched off, provided the
V
BAT
supply is maintained.
• If LSI is selected as the RTC clock:
– The RTC state is not guaranteed if the V
DD
supply is powered off.
• If the HSE clock divided by a prescaler is used as the RTC clock:
– The RTC state is not guaranteed if the V
DD
supply is powered off or if the internal
voltage regulator is powered off (removing power from the V
CORE
domain).
When the RTC clock is LSE or LSI, the RTC remains clocked and functional under system
reset.
5.2.13 Timer clock
The timer clock TIMPCLK is derived from PCLK (used for APB) as follows:
1. If the APB prescaler is set to 1, TIMPCLK frequency is equal to PCLK frequency.
2. Otherwise, the TIMPCLK frequency is set to twice the PCLK frequency.
For TIM1 and TIM15, PLLQCLK clock can also be selected, if:
• PCLK is derived from PLLRCLK, and
• PLLQCLK frequency is an integer multiplication by 2 or more of the PCLK frequency,
without exceeding 128 MHz.
5.2.14 Watchdog clock
If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
5.2.15 Clock-out capability
MCO and MCO2
The MCO and MCO2 pins output, independently of each other, the clock selected from:
• LSI
• LSE
• SYSCLK
• HSI16
• HSI48
• HSE
• PLLPCLK
• PLLQCLK
• PLLRCLK
• RTCCLK
• RTC WAKEUP
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