ST STM32G0 1 Series

DMA request multiplexer (DMAMUX) RM0444
300/1390 RM0444 Rev 5
Table 52. DMAMUX: assignment of multiplexer inputs to resources
DMA
request
MUX
input
Resource
DMA
request
MUX
input
Resource
DMA
request
MUX
input
Resource
1 dmamux_req_gen0 27 TIM2_CH2 53 USART2_TX
2 dmamux_req_gen1 28 TIM2_CH3 54 USART3_RX
3 dmamux_req_gen2 29 TIM2_CH4 55 USART3_TX
4 dmamux_req_gen3 30 TIM2_TRIG 56 USART4_RX
5 ADC 31 TIM2_UP 57 USART4_TX
6 AES_IN 32 TIM3_CH1 58 UCPD1_RX
7 AES_OUT 33 TIM3_CH2 59 UCPD1_TX
8 DAC_Channel1 34 TIM3_CH3 60 UCPD2_RX
9 DAC_Channel2 35 TIM3_CH4 61 UCPD2_TX
10 I2C1_RX 36 TIM3_TRIG 62 I2C3_RX
11 I2C1_TX 37 TIM3_UP 63 I2C3_TX
12 I2C2_RX 38 TIM6_UP 64 LPUART2_RX
13 I2C2_TX 39 TIM7_UP 65 LPUART2_TX
14 LPUART_RX 40 TIM15_CH1 66 SPI3_RX
15 LPUART_TX 41 TIM15_CH2 67 SPI3_TX
16 SPI1_RX 42 TIM15_TRIG_COM 68 TIM4_CH1
17 SPI1_TX 43 TIM15_UP 69 TIM4_CH2
18 SPI2_RX 44 TIM16_CH1 70 TIM4_CH3
19 SPI2_TX 45 TIM16_COM 71 TIM4_CH4
20 TIM1_CH1 46 TIM16_UP 72 TIM4_TRIG
21 TIM1_CH2 47 TIM17_CH1 73 TIM4_UP
22 TIM1_CH3 48 TIM17_COM 74 USART5_RX
23 TIM1_CH4 49 TIM17_UP 75 USART5_TX
24 TIM1_TRIG_COM 50 USART1_RX 76 USART6_RX
25 TIM1_UP 51 USART1_TX 77 USART6_TX
26 TIM2_CH1 52 USART2_RX - -
Table 53. DMAMUX: assignment of trigger inputs to resources
Trigger input Resource Trigger input Resource
0 EXTI LINE0 12 EXTI LINE12
1 EXTI LINE1 13 EXTI LINE13
2 EXTI LINE2 14 EXTI LINE14
3 EXTI LINE3 15 EXTI LINE15
4 EXTI LINE4 16 dmamux_evt0
5 EXTI LINE5 17 dmamux_evt1